-------------------------------------------------------------------------------
-- File : ConfigV1d.vhd
-- address decoding above 1.5MB ignored --21July2004
--
-- File : Config_V1c.vhd --09 march 2004
-- File : Config_V1b.vhd
-- Date : 11 September 2003
-- Last update details:
-- 15 Sep 2003,
-- 03 March 2004, 04 Mar '04, 5Mar04 ---- TP, KPA
-- LA is latched now 15MAR04
-- 04 Mar '04: LA_31 is latched before decoding the address
-- LCLK2 (instead of clk20) latches the LAD address - TP, KPA
-- 05 mar '04: LCLK2 (instead of clk20) used in C_PEN generation,
-- now READY2 generation is after COUNT2 == 3 -TP, KPA
-- 06 MAR '04: working on improving the DR latch control,
-- signal READYint is introduced,
-- READY generation
-- 09 MAR '04 :Working on CLK10 generation - kpa, tp
-------------------------------------------------------------------------------
-- Description: To configure FPGA1 (TRANSACT FPGA) and FPGA2 (PROCESS FPGA)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ConfigV1d is
port (
LCLK2 : in std_logic; -- from Clk Driver(pin-5) -> CPLD(pin 17)
LRESETo : in std_logic; -- from PLX(pin-152) -> CPLD(pin-48)
LW_R : in std_logic; -- from PLX(pin-90) -> CPLD(pin-43)
ADS : in std_logic; -- from PLX(pin-145) -> CPLD(pin-47)
LHOLD : in std_logic; -- from PLX(pin-143) -> CPLD(pin-45)
LHOLDA : out std_logic; -- to PLX(pin-144) <- CPLD(pin-46)
READY : buffer std_logic; -- to PLX(pin-135) <- CPLD(pin-44)
LA_31 : in std_logic; -- from PLX
LA : in std_logic_vector(20 downto 19); -- from PLX
LAD : inout std_logic_vector(15 downto 0); -- from/to PLX
INIT1 : in std_logic; --|
DONE1 : in std_logic; --| Configuration pins of
PRG1 : out std_logic; --| FPGA1 (TRANSACT FPGA)
DIN1 : out std_logic; --|
CCLK1 : out std_logic; --|
INIT2 : in std_logic; --|
DONE2 : in std_logic; --| Configuration pins of
PRG2 : out std_logic; --| FPGA2 (PROCESS FPGA)
DIN2 : out std_logic; --|
CCLK2 : out std_logic; --|
CS0_F1 : buffer std_logic; --| for TRANSACT FPGA
CS0_F2 : buffer std_logic; --| for PROCESS FPGA
CS1_F2 : buffer std_logic; --| for RAMS
C_LED : out std_logic; --| Just for monitoring! CPLD(pin-9)
XTALIN : in std_logic; -- from Oscillator -> CPLD(pin-15)
CLKOUT : out std_logic; -- to Clock Driver(pin-1) <- CPLD(pin-8)
GP3 : out std_logic;
GP4 :out std_logic
);
end ConfigV1d;
architecture aConfigV1d of ConfigV1d is
signal resetb : std_logic;
signal scsa : std_logic;
signal cpld_cs : std_logic;
signal cs0_f1b : std_logic;
signal cs0_f2b : std_logic;
signal cs1_f2b : std_logic;
signal cpld_cr : std_logic;
signal c_pen : std_logic;
signal c_penb : std_logic;
signal cpld_dr : std_logic;
signal cpld_srd : std_logic;
signal cpld_sr : std_logic;
signal clk10 : std_logic;
signal clk10b : std_logic;
signal clk20 : std_logic;
signal clk20b : std_logic;
signal l_s : std_logic;
signal readyi1 : std_logic;
signal readyi2 : std_logic;
signal ce : std_logic;
signal ad : std_logic_vector(14 downto 0);
signal dr : std_logic_vector(15 downto 0);
signal count1 : std_logic_vector(3 downto 0);
signal count2 : std_logic_vector(4 downto 0);
signal cr : std_logic_vector(1 downto 0);
signal a20a19 : std_logic_vector(1 downto 0);
signal a31 : std_logic;
signal READYint : std_logic; -- 6 mar 04 kpa, tp
signal fpga_cs : std_logic; --do--
begin
CS0_F1 <= cs0_f1b;
CS0_F2 <= cs0_f2b;
CS1_F2 <= cs1_f2b;
clk10b <= not clk10;
clk20b <= not clk20;
c_penb <= not c_pen;
LHOLDA <= LHOLD;
CLKOUT <= XTALIN;
resetb <= not LRESETo;
ce <= ADS and READYint;
C_LED <= scsa; -- monitored for diagnostics 06 mar 04 KPA, TP
GP3 <= c_pen; -- --------- do ------------
GP4 <= clk10; -- --------- do ------------
-----------------------------------------------------------------------------
-- address decoder and ready generation
-----------------------------------------------------------------------------
-- csa
scsa <= '1' when (a31 = '0' and c_pen = '1') else
'0';
-- add_latch
latch: process(LCLK2) -- 04 March 04
begin
if LCLK2'event and LCLK2 = '1' then
if ADS = '0' then
ad <= LAD(15 downto 1);
a20a19 <= LA;
a31 <= LA_31;
else
ad <= ad;
a20a19 <= a20a19;
a31 <= a31;
end if;
end if;
end process latch;
-------------------------------------------------------------------------------
-- 2_4 decoder 1 --generation of chip selects address Range
-------------------------------------------------------------------------------
cpld_cs <= '1' when (a20a19 = "00" and scsa = '1') else '0'; -- 0 to (512K-1)
cs0_f1b <= '1' when (a20a19 = "01" and scsa = '1') else '0'; -- 512K to (1M-1)
cs0_f2b <= '1' when (a20a19 = "10" and scsa = '1') else '0'; -- 1M to (1.5M -1)
cs1_f2b <= '1' when (a20a19 = "11" and scsa = '1') else '0'; -- 1.5M to (2M-1)
fpga_cs <= (cs0_f1b or cs0_f2b ); --or cs1_f2b);
-----------------------------------------------------------------------------
-- C_PEN : generation of c_pen signal
-----------------------------------------------------------------------------
process (LCLK2, resetb)
begin -- process
if resetb = '1' then
c_pen <= '0';
elsif LCLK2'event and LCLK2 = '1' then -- rising clock edge
if ce = '0' then
c_pen <= c_penb;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- 2_4 decoder 2 :::: NOW lad[3:0]=0000 not decoded
-----------------------------------------------------------------------------
cpld_cr <= '1' when (ad(2 downto 0) = "100" and cpld_cs = '1' and LW_R = '1')else
'0';
cpld_dr <= '1' when (ad(2 downto 0) = "010" and cpld_cs = '1' and LW_R = '1')else
'0';
cpld_sr <= '1' when (ad(2 downto 0) = "110" and cpld_cs = '1' and LW_R = '0')else
'0';
-----------------------------------------------------------------------------
--COUNT1 : 4 - bit counter
-----------------------------------------------------------------------------
counter1: process (clk10b, resetb)
begin -- process counter1
if resetb = '1' then
count1 <= (others => '0');
elsif clk10b'event and clk10b = '1' then -- rising clock edge
count1 <= count1 + '1';
end if;
end process counter1;
-----------------------------------------------------------------------------
-- generation of readyi1
-----------------------------------------------------------------------------
--COUNT2 : 3-bit counter
-----------------------------------------------------------------------------
process (clk20b, resetb)
begin -- process
if resetb = '1' then
count2 <= (others => '0');
elsif clk20b'event and clk20b = '1' then
if c_pen = '1' then
count2 <= count2 + '1';
else
count2 <= "00000";
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- generation of readyi2
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
--readyi1 <= '0' when (count2 = "11111" and cpld_dr ='1') else '1';
readyi1 <= '0' when (count2 = "11111" and cpld_cs ='1') else '1';
-- readyi2 <= '0' when (count2 ="00011" and cpld_dr = '0') else '1' ;
readyi2 <= '0' when (count2 ="00011" and fpga_cs = '1') else '1' ;
-----------------------------------------------------------------------------
-- generation of ready
-----------------------------------------------------------------------------
READYint <= readyi1 and readyi2; -- 6 Mar 04 kpa, tp
READY <= '0' when (READYint = '0' ) else 'Z';
-- READY <= '0' when (readyi1 ='0' or readyi2 = '0') else 'Z';
-----------------------------------------------------------------------------
-- generation of l_s
-----------------------------------------------------------------------------
l_s <= '0' when count1 ="0000" else '1';
-----------------------------------------------------------------------------
--CLK20 : generation of clk20
-----------------------------------------------------------------------------
p1: process (LCLK2, resetb)
begin -- process p1
if resetb = '1' then
clk20 <= '0';
elsif LCLK2'event and LCLK2 = '1' then -- rising clock edge
clk20 <= clk20b;
end if;
end process p1;
-------------------------------------------------------------------------------
--CLK10 : generation of clk10
-------------------------------------------------------------------------------
process (clk20, resetb)
begin -- process
if resetb = '1' then
clk10 <= '0';
elsif clk20'event and clk20 = '1' then -- rising clock edge
if cpld_dr = '1' or count1 /= "0000" then
clk10 <= clk10b;
else
clk10 <= clk10;
end if;
end if;
end process;
-----------------------------------------------------------------------------
--DR : data register
------------------------------------------------------------------------------
data_reg: process (clk10, resetb)
begin -- process data_reg
if resetb = '1' then -- asynchronous reset (active low)
dr <= (others => '0');
elsif clk10'event and clk10 = '1' then -- rising clock edge
if l_s = '0' then
dr <= LAD;
else
dr(14 downto 0) <= dr(15 downto 1);
end if;
end if;
end process data_reg;
-------------------------------------------------------------------------------
--CR : control register
-------------------------------------------------------------------------------
process (clk20, resetb)
begin -- process
if resetb = '1' then
cr <= (others => '1');
elsif clk20'event and clk20 = '1' then -- rising clock edge
if cpld_cr ='1' then
cr <= LAD(1 downto 0);
end if;
end if;
end process;
-----------------------------------------------------------------------------
--SR : srd_latch
-----------------------------------------------------------------------------
srd_latch: process (clk20)
begin -- process srd_latch
if clk20'event and clk20 = '1' then -- rising clock edge
cpld_srd <= cpld_sr;
end if;
end process srd_latch;
-----------------------------------------------------------------------------
-- status register
-----------------------------------------------------------------------------
--process (clk20)
--begin -- process
-- if clk20'event and clk20 = '1' then -- rising clock edge
LAD(7 downto 0) <= ('0', '0', cr(1), cr(0), INIT2, DONE2, INIT1, DONE1)
when cpld_srd = '1'
else (others => 'Z');
-- end if;
--end process;
-------------------------------------------------------------------------------
-- tristated o/ps
-------------------------------------------------------------------------------
DIN1 <= dr(0) when cr = "11" else 'Z';
DIN2 <= dr(0) when cr = "10" else 'Z';
PRG1 <= '0' when cr = "01" else 'Z';
PRG2 <= '0' when cr = "00" else 'Z';
CCLK1 <= clk10b when cr = "11" else 'Z';
CCLK2 <= clk10b when cr = "10" else 'Z';
end aConfigV1d;