----------------------------------------------------------------
-- FILE : all_LV_lines_v1.vhd
-- Created : 17 Sep 2004 - last modified 21sep04 TP
-- Routes most of the Type-A and Type-C signals to TRANSACT FB(24 downto 0) lines -TP, KPA
-- 
-- ----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity all_LV_lines_v1 is
    Port (  
	        LCLK3 : in std_logic;
		     PKLED : out std_logic;
           LV    : IN STD_LOGIC_VECTOR(0 TO 11);
           RSI   : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
           FB    : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
           
          );
end all_LV_lines_v1;

architecture aall_LV_lines_v1 of all_LV_lines_v1 is
   

signal clkint, clk20, clk20b : std_logic;
signal count5 : std_logic_vector (31 downto 0):= (others => '0');
signal LED : std_logic := '0';
SIGNAL LVDS_IN : STD_LOGIC_VECTOR(11 DOWNTO 0);

begin
--STANDARD_DIAG-------------------------------------------------------
clkint  <= clk20b;  --FB24;
clk20b <= not clk20;
PKLED  <= LED;

-------------------------------------------------------------------
-- Divide by 2 of LCLK3 -40 MHz
-------------------------------------------------------------------
p1: process (LCLK3)
  begin  -- process p1
          
    if LCLK3'event and LCLK3 = '1' then  -- rising clock edge
      clk20 <= clk20b;
    end if;
  end process p1;

---------------------------------------------------------------
-- 			5-bit counter
---------------------------------------------------------------	
   process(clkint)
   begin    
      if clkint'event and clkint = '1' then  -- rising clock edge
        count5 <= count5 + '1';
    --   if count5 = "10011" then
       if count5(31) = '1' then
           LED <= not LED;
           count5 <= (others =>'0');
       end if;
      end if;
  end process;
---------------------------------------------------------------

--STANDARD_DIAG END---------------------------------------------------

 -- arrange the LV inputs in sequence ---
  LVDS_IN(0) <= LV(11 );
  LVDS_IN(1) <= LV(10 );
  LVDS_IN(2) <= LV(9 );
  LVDS_IN(3) <= LV(8 );
  LVDS_IN(4) <= LV(7 );
  LVDS_IN(5) <= LV(6 );
  LVDS_IN(6) <= LV(5 );
  LVDS_IN(7) <= LV(4 );
  LVDS_IN(8) <= LV(3 );
  LVDS_IN(9) <= LV(2 );
  LVDS_IN(10) <= LV(1 );
  LVDS_IN(11) <= LV(0 );
 -------------------------------------- 
  
  
  --FB(5 DOWNTO 1) <= LVDS_IN(4 DOWNTO 0); 

     -------------------------------------- refer PLX LOG of 17/Sep/04
      --Inputs from Type-C Connector
     -- reversing the order to suit the ADC coonectos

     --LV input-1 (Top most)
     FB(3 DOWNTO 0) <= LV(8 TO 11); 
  
     --LV input-2  (Top but one)
     FB(7 DOWNTO 4) <= LV(4 TO 7); 

     --LV input-3  (bottom but one)
     FB(11 DOWNTO 8) <= LV(0 TO 3); 

    -------------------------------------- refer PLX LOG of 17/Sep/04
    --Inputs From 68pin connector (Type-A)

    --LV input-4
     FB(15 DOWNTO 12) <= RSI(3 DOWNTO 0);
    
     --LV input-5
     FB(19 DOWNTO 16) <= RSI(7 DOWNTO 4); 
  
     --LV input-6
     FB(23 DOWNTO 20) <= RSI(19 DOWNTO 16);
     -------------------------------------

     --STROBE from ADC
     FB(24) <= RSI(8); 


end aall_LV_lines_v1;