----------------------------------------------------------------
-- FILE : pack_V2.vhd
-- Last update : 03 June 2004
-- Routing the Type-C signals to TRANSACT   -TP, KPA
-- 
-- previous Update : 15 Apr 2004: Receives 10MHz clk at FB0
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PACK_V2 is
    Port ( FB0   : in std_logic;
	        LCLK3 : in std_logic;
		     PKLED : out std_logic;
           LV    : IN STD_LOGIC_VECTOR(7 TO 11);
           FB    : OUT STD_LOGIC_VECTOR(5 DOWNTO 1)
           
			 );
end PACK_V2;

architecture aPACK_V2 of PACK_V2 is
   

signal clk10, clk20, clk20b : std_logic;
signal count5 : std_logic_vector (21 downto 0):= (others => '0');
signal LED : std_logic := '0';
SIGNAL LVDS_IN : STD_LOGIC_VECTOR(11 DOWNTO 0);

begin
--STANDARD_DIAG-------------------------------------------------------
clk10  <= FB0;
clk20b <= not clk20;
PKLED  <= LED;

-------------------------------------------------------------------
-- Divide by 2 of LCLK3 -40 MHz
-------------------------------------------------------------------
p1: process (LCLK3)
  begin  -- process p1
          
    if LCLK3'event and LCLK3 = '1' then  -- rising clock edge
      clk20 <= clk20b;
    end if;
  end process p1;

---------------------------------------------------------------
-- 			5-bit counter
---------------------------------------------------------------	
   process(clk10)
	begin    
      if clk10'event and clk10 = '1' then  -- rising clock edge
        count5 <= count5 + '1';
    --   if count5 = "10011" then
			 if count5(21) = '1' then
	        LED <= not LED;
			  count5 <= (others =>'0');
		  end if;
      end if;
  end process;
---------------------------------------------------------------

--STANDARD_DIAG END---------------------------------------------------

 -- arrange the LV inputs in sequence ---
  LVDS_IN(0) <= LV(11 );
  LVDS_IN(1) <= LV(10 );
  LVDS_IN(2) <= LV(9 );
  LVDS_IN(3) <= LV(8 );
  LVDS_IN(4) <= LV(7 );
--  LVDS_IN(5) <= LV(6 );
--  LVDS_IN(6) <= LV(5 );
--  LVDS_IN(7) <= LV(4 );
--  LVDS_IN(8) <= LV(3 );
--  LVDS_IN(9) <= LV(2 );
--  LVDS_IN(10) <= LV(1 );
--  LVDS_IN(11) <= LV(0 );
 -------------------------------------- 
  
  
  --FB(5 DOWNTO 1) <= LVDS_IN(4 DOWNTO 0); 
  FB(5 DOWNTO 1) <= LV(7 TO 11); 
   

end aPACK_V2;