 
cpldfit:  version E.38                              Xilinx Inc.
                                  Fitter Report
Design Name: pack_v2                             Date:  7- 3-2004,  3:56PM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
28 /144 ( 19%) 72  /720  ( 10%) 23 /144 ( 15%) 12 /117 ( 10%) 46 /432 ( 10%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    6           6    |  I/O              :    10       99
Output        :    6           6    |  GCK/IO           :     2        1
Bidirectional :    0           0    |  GTS/IO           :     0        4
GCK           :    0           0    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     12          12

MACROCELL RESOURCES:

Total Macrocells Available                   144
Registered Macrocells                         23
Non-registered Macrocell driving I/O           5

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 28 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 28 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:Cpld:1218 - Removing unused input(s) 'lclk3'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
count5<0>           2       3       FB1_10  STD       31   I/O       (b)
count5<10>          3       13      FB2_18  STD            (b)       (b)
count5<11>          3       14      FB2_17  STD       15   I/O       (b)
count5<12>          3       15      FB2_16  STD       14   I/O       (b)
count5<13>          3       16      FB2_13  STD       12   I/O       I
count5<14>          3       17      FB2_9   STD       6    GTS/I/O   (b)
count5<15>          3       18      FB1_18  STD            (b)       (b)
count5<16>          3       19      FB1_17  STD       30   GCK/I/O   (b)
count5<17>          3       20      FB1_16  STD       35   I/O       (b)
count5<18>          3       21      FB1_15  STD       28   I/O       (b)
count5<19>          3       22      FB1_14  STD       27   I/O       (b)
count5<1>           3       4       FB1_13  STD            (b)       (b)
count5<20>          3       23      FB1_12  STD       26   I/O       (b)
count5<21>          2       23      FB1_9   STD       22   I/O       (b)
count5<2>           3       5       FB1_11  STD       24   I/O       (b)
count5<3>           3       6       FB2_8   STD       5    GTS/I/O   (b)
count5<4>           3       7       FB2_7   STD            (b)       (b)
count5<5>           3       8       FB2_6   STD       3    GTS/I/O   (b)
count5<6>           3       9       FB2_5   STD       2    GTS/I/O   (b)
count5<7>           3       10      FB2_3   STD            (b)       (b)
count5<8>           3       11      FB2_2   STD       143  GSR/I/O   (b)
count5<9>           3       12      FB2_1   STD       142  I/O       (b)
fb<1>               1       1       FB2_14  STD  FAST 11   I/O       O
fb<2>               1       1       FB2_12  STD  FAST 10   I/O       O
fb<3>               1       1       FB2_11  STD  FAST 9    I/O       O
fb<4>               1       1       FB2_10  STD  FAST 7    I/O       O
fb<5>               1       1       FB2_4   STD  FAST 4    I/O       O
pkled               3       3       FB2_15  STD  FAST 13   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
fb0                                 FB2_13            12   I/O       I
lv<10>                              FB3_8             38   GCK/I/O   I
lv<11>                              FB3_5             33   I/O       I
lv<7>                               FB3_1             39   I/O       I
lv<8>                               FB3_2             32   GCK/I/O   I
lv<9>                               FB3_6             34   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          10          23          23           28         0/0       15   
FB2          18          23          23           44         6/0       15   
FB3           0           0           0            0         0/0       15   
FB4           0           0           0            0         0/0       15   
FB5           0           0           0            0         0/0       14   
FB6           0           0           0            0         0/0       13   
FB7           0           0           0            0         0/0       15   
FB8           0           0           0            0         0/0       15   
            ----                                -----       -----     ----- 
             28                                   72         6/0      117   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               23/31
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1         23    I/O     
(unused)              0       0     0   5     FB1_2         16    I/O     
(unused)              0       0     0   5     FB1_3         17    I/O     
(unused)              0       0     0   5     FB1_4         25    I/O     
(unused)              0       0     0   5     FB1_5         19    I/O     
(unused)              0       0     0   5     FB1_6         20    I/O     
(unused)              0       0     0   5     FB1_7               (b)     
(unused)              0       0     0   5     FB1_8         21    I/O     
count5<21>            2       0     0   3     FB1_9   STD   22    I/O     (b)
count5<0>             2       0     0   3     FB1_10  STD   31    I/O     (b)
count5<2>             3       0     0   2     FB1_11  STD   24    I/O     (b)
count5<20>            3       0     0   2     FB1_12  STD   26    I/O     (b)
count5<1>             3       0     0   2     FB1_13  STD         (b)     (b)
count5<19>            3       0     0   2     FB1_14  STD   27    I/O     (b)
count5<18>            3       0     0   2     FB1_15  STD   28    I/O     (b)
count5<17>            3       0     0   2     FB1_16  STD   35    I/O     (b)
count5<16>            3       0     0   2     FB1_17  STD   30    GCK/I/O (b)
count5<15>            3       0     0   2     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: fb0                9: "count5<16>"      17: "count5<3>" 
  2: "count5<0>"       10: "count5<17>"      18: "count5<4>" 
  3: "count5<10>"      11: "count5<18>"      19: "count5<5>" 
  4: "count5<11>"      12: "count5<19>"      20: "count5<6>" 
  5: "count5<12>"      13: "count5<1>"       21: "count5<7>" 
  6: "count5<13>"      14: "count5<20>"      22: "count5<8>" 
  7: "count5<14>"      15: "count5<21>"      23: "count5<9>" 
  8: "count5<15>"      16: "count5<2>"      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
count5<21>           XXXXXXXXXXXXXXXXXXXXXXX................. 23      23
count5<0>            XX............X......................... 3       3
count5<2>            XX..........X.XX........................ 5       5
count5<20>           XXXXXXXXXXXXXXXXXXXXXXX................. 23      23
count5<1>            XX..........X.X......................... 4       4
count5<19>           XXXXXXXXXXXXX.XXXXXXXXX................. 22      22
count5<18>           XXXXXXXXXXX.X.XXXXXXXXX................. 21      21
count5<17>           XXXXXXXXXX..X.XXXXXXXXX................. 20      20
count5<16>           XXXXXXXXX...X.XXXXXXXXX................. 19      19
count5<15>           XXXXXXXX....X.XXXXXXXXX................. 18      18
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               23/31
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
count5<9>             3       0     0   2     FB2_1   STD   142   I/O     (b)
count5<8>             3       0     0   2     FB2_2   STD   143   GSR/I/O (b)
count5<7>             3       0     0   2     FB2_3   STD         (b)     (b)
fb<5>                 1       0     0   4     FB2_4   STD   4     I/O     O
count5<6>             3       0     0   2     FB2_5   STD   2     GTS/I/O (b)
count5<5>             3       0     0   2     FB2_6   STD   3     GTS/I/O (b)
count5<4>             3       0     0   2     FB2_7   STD         (b)     (b)
count5<3>             3       0     0   2     FB2_8   STD   5     GTS/I/O (b)
count5<14>            3       0     0   2     FB2_9   STD   6     GTS/I/O (b)
fb<4>                 1       0     0   4     FB2_10  STD   7     I/O     O
fb<3>                 1       0     0   4     FB2_11  STD   9     I/O     O
fb<2>                 1       0     0   4     FB2_12  STD   10    I/O     O
count5<13>            3       0     0   2     FB2_13  STD   12    I/O     I
fb<1>                 1       0     0   4     FB2_14  STD   11    I/O     O
pkled                 3       0     0   2     FB2_15  STD   13    I/O     O
count5<12>            3       0     0   2     FB2_16  STD   14    I/O     (b)
count5<11>            3       0     0   2     FB2_17  STD   15    I/O     (b)
count5<10>            3       0     0   2     FB2_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: fb0                9: "count5<11>"      17: "count5<4>" 
  2: "lv<11>"          10: "count5<12>"      18: "count5<5>" 
  3: "lv<10>"          11: "count5<13>"      19: "count5<6>" 
  4: "lv<9>"           12: "count5<14>"      20: "count5<7>" 
  5: "lv<8>"           13: "count5<1>"       21: "count5<8>" 
  6: "lv<7>"           14: "count5<21>"      22: "count5<9>" 
  7: "count5<0>"       15: "count5<2>"       23: pkled 
  8: "count5<10>"      16: "count5<3>"      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
count5<9>            X.....X.....XXXXXXXXXX.................. 12      12
count5<8>            X.....X.....XXXXXXXXX................... 11      11
count5<7>            X.....X.....XXXXXXXX.................... 10      10
fb<5>                .....X.................................. 1       1
count5<6>            X.....X.....XXXXXXX..................... 9       9
count5<5>            X.....X.....XXXXXX...................... 8       8
count5<4>            X.....X.....XXXXX....................... 7       7
count5<3>            X.....X.....XXXX........................ 6       6
count5<14>           X.....XXXXXXXXXXXXXXXX.................. 17      17
fb<4>                ....X................................... 1       1
fb<3>                ...X.................................... 1       1
fb<2>                ..X..................................... 1       1
count5<13>           X.....XXXXX.XXXXXXXXXX.................. 16      16
fb<1>                .X...................................... 1       1
pkled                X............X........X................. 3       3
count5<12>           X.....XXXX..XXXXXXXXXX.................. 15      15
count5<11>           X.....XXX...XXXXXXXXXX.................. 14      14
count5<10>           X.....XX....XXXXXXXXXX.................. 13      13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1         39    I/O     I
(unused)              0       0     0   5     FB3_2         32    GCK/I/O I
(unused)              0       0     0   5     FB3_3         41    I/O     
(unused)              0       0     0   5     FB3_4         44    I/O     
(unused)              0       0     0   5     FB3_5         33    I/O     I
(unused)              0       0     0   5     FB3_6         34    I/O     I
(unused)              0       0     0   5     FB3_7         46    I/O     
(unused)              0       0     0   5     FB3_8         38    GCK/I/O I
(unused)              0       0     0   5     FB3_9         40    I/O     
(unused)              0       0     0   5     FB3_10        48    I/O     
(unused)              0       0     0   5     FB3_11        43    I/O     
(unused)              0       0     0   5     FB3_12        45    I/O     
(unused)              0       0     0   5     FB3_13              (b)     
(unused)              0       0     0   5     FB3_14        49    I/O     
(unused)              0       0     0   5     FB3_15        50    I/O     
(unused)              0       0     0   5     FB3_16              (b)     
(unused)              0       0     0   5     FB3_17        51    I/O     
(unused)              0       0     0   5     FB3_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1         118   I/O     
(unused)              0       0     0   5     FB4_2         126   I/O     
(unused)              0       0     0   5     FB4_3         133   I/O     
(unused)              0       0     0   5     FB4_4               (b)     
(unused)              0       0     0   5     FB4_5         128   I/O     
(unused)              0       0     0   5     FB4_6         129   I/O     
(unused)              0       0     0   5     FB4_7               (b)     
(unused)              0       0     0   5     FB4_8         130   I/O     
(unused)              0       0     0   5     FB4_9         131   I/O     
(unused)              0       0     0   5     FB4_10        135   I/O     
(unused)              0       0     0   5     FB4_11        132   I/O     
(unused)              0       0     0   5     FB4_12        134   I/O     
(unused)              0       0     0   5     FB4_13        137   I/O     
(unused)              0       0     0   5     FB4_14        136   I/O     
(unused)              0       0     0   5     FB4_15        138   I/O     
(unused)              0       0     0   5     FB4_16        139   I/O     
(unused)              0       0     0   5     FB4_17        140   I/O     
(unused)              0       0     0   5     FB4_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB5_1               (b)     
(unused)              0       0     0   5     FB5_2         52    I/O     
(unused)              0       0     0   5     FB5_3         59    I/O     
(unused)              0       0     0   5     FB5_4               (b)     
(unused)              0       0     0   5     FB5_5         53    I/O     
(unused)              0       0     0   5     FB5_6         54    I/O     
(unused)              0       0     0   5     FB5_7         66    I/O     
(unused)              0       0     0   5     FB5_8         56    I/O     
(unused)              0       0     0   5     FB5_9         57    I/O     
(unused)              0       0     0   5     FB5_10        68    I/O     
(unused)              0       0     0   5     FB5_11        58    I/O     
(unused)              0       0     0   5     FB5_12        60    I/O     
(unused)              0       0     0   5     FB5_13        70    I/O     
(unused)              0       0     0   5     FB5_14        61    I/O     
(unused)              0       0     0   5     FB5_15        64    I/O     
(unused)              0       0     0   5     FB5_16              (b)     
(unused)              0       0     0   5     FB5_17        69    I/O     
(unused)              0       0     0   5     FB5_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB6_1               (b)     
(unused)              0       0     0   5     FB6_2         106   I/O     
(unused)              0       0     0   5     FB6_3               (b)     
(unused)              0       0     0   5     FB6_4         111   I/O     
(unused)              0       0     0   5     FB6_5         110   I/O     
(unused)              0       0     0   5     FB6_6         112   I/O     
(unused)              0       0     0   5     FB6_7               (b)     
(unused)              0       0     0   5     FB6_8         113   I/O     
(unused)              0       0     0   5     FB6_9         116   I/O     
(unused)              0       0     0   5     FB6_10        115   I/O     
(unused)              0       0     0   5     FB6_11        119   I/O     
(unused)              0       0     0   5     FB6_12        120   I/O     
(unused)              0       0     0   5     FB6_13              (b)     
(unused)              0       0     0   5     FB6_14        121   I/O     
(unused)              0       0     0   5     FB6_15        124   I/O     
(unused)              0       0     0   5     FB6_16        117   I/O     
(unused)              0       0     0   5     FB6_17        125   I/O     
(unused)              0       0     0   5     FB6_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB7_1               (b)     
(unused)              0       0     0   5     FB7_2         71    I/O     
(unused)              0       0     0   5     FB7_3         75    I/O     
(unused)              0       0     0   5     FB7_4               (b)     
(unused)              0       0     0   5     FB7_5         74    I/O     
(unused)              0       0     0   5     FB7_6         76    I/O     
(unused)              0       0     0   5     FB7_7         77    I/O     
(unused)              0       0     0   5     FB7_8         78    I/O     
(unused)              0       0     0   5     FB7_9         80    I/O     
(unused)              0       0     0   5     FB7_10        79    I/O     
(unused)              0       0     0   5     FB7_11        82    I/O     
(unused)              0       0     0   5     FB7_12        85    I/O     
(unused)              0       0     0   5     FB7_13        81    I/O     
(unused)              0       0     0   5     FB7_14        86    I/O     
(unused)              0       0     0   5     FB7_15        87    I/O     
(unused)              0       0     0   5     FB7_16        83    I/O     
(unused)              0       0     0   5     FB7_17        88    I/O     
(unused)              0       0     0   5     FB7_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB8_1               (b)     
(unused)              0       0     0   5     FB8_2         91    I/O     
(unused)              0       0     0   5     FB8_3         95    I/O     
(unused)              0       0     0   5     FB8_4         97    I/O     
(unused)              0       0     0   5     FB8_5         92    I/O     
(unused)              0       0     0   5     FB8_6         93    I/O     
(unused)              0       0     0   5     FB8_7               (b)     
(unused)              0       0     0   5     FB8_8         94    I/O     
(unused)              0       0     0   5     FB8_9         96    I/O     
(unused)              0       0     0   5     FB8_10        101   I/O     
(unused)              0       0     0   5     FB8_11        98    I/O     
(unused)              0       0     0   5     FB8_12        100   I/O     
(unused)              0       0     0   5     FB8_13        103   I/O     
(unused)              0       0     0   5     FB8_14        102   I/O     
(unused)              0       0     0   5     FB8_15        104   I/O     
(unused)              0       0     0   5     FB8_16        107   I/O     
(unused)              0       0     0   5     FB8_17        105   I/O     
(unused)              0       0     0   5     FB8_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 "fb<1>"  =  "lv<11>"    

 "fb<2>"  =  "lv<10>"    

 "fb<3>"  =  "lv<9>"    

 "fb<4>"  =  "lv<8>"    

 "fb<5>"  =  "lv<7>"    

 "count5<0>"  :=  /"count5<21>" * /"count5<0>"
    "count5<0>".CLKF  =  fb0
    "count5<0>".PRLD  =  GND    

 "count5<10>".T  =  "count5<21>" * "count5<10>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>"
    "count5<10>".CLKF  =  fb0
    "count5<10>".PRLD  =  GND    

 "count5<11>".T  =  "count5<21>" * "count5<11>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>"
    "count5<11>".CLKF  =  fb0
    "count5<11>".PRLD  =  GND    

 "count5<12>".T  =  "count5<21>" * "count5<12>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>"
    "count5<12>".CLKF  =  fb0
    "count5<12>".PRLD  =  GND    

 "count5<13>".T  =  "count5<21>" * "count5<13>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>"
    "count5<13>".CLKF  =  fb0
    "count5<13>".PRLD  =  GND    

 "count5<14>".T  =  "count5<21>" * "count5<14>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>"
    "count5<14>".CLKF  =  fb0
    "count5<14>".PRLD  =  GND    

 "count5<15>".T  =  "count5<21>" * "count5<15>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>"
    "count5<15>".CLKF  =  fb0
    "count5<15>".PRLD  =  GND    

 "count5<16>".T  =  "count5<21>" * "count5<16>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>" * "count5<15>"
    "count5<16>".CLKF  =  fb0
    "count5<16>".PRLD  =  GND    

 "count5<17>".T  =  "count5<21>" * "count5<17>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>" * "count5<15>" * "count5<16>"
    "count5<17>".CLKF  =  fb0
    "count5<17>".PRLD  =  GND    

 "count5<18>".T  =  "count5<21>" * "count5<18>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>" * "count5<15>" * "count5<16>" * "count5<17>"
    "count5<18>".CLKF  =  fb0
    "count5<18>".PRLD  =  GND    

 "count5<19>".T  =  "count5<21>" * "count5<19>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>" * "count5<15>" * "count5<16>" * "count5<17>" * 
	"count5<18>"
    "count5<19>".CLKF  =  fb0
    "count5<19>".PRLD  =  GND    

 "count5<1>"  :=  /"count5<21>" * "count5<0>" * /"count5<1>"
	+ /"count5<21>" * /"count5<0>" * "count5<1>"
    "count5<1>".CLKF  =  fb0
    "count5<1>".PRLD  =  GND    

 "count5<20>".T  =  "count5<21>" * "count5<20>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>" * "count5<15>" * "count5<16>" * "count5<17>" * 
	"count5<18>" * "count5<19>"
    "count5<20>".CLKF  =  fb0
    "count5<20>".PRLD  =  GND    

 "count5<21>"  :=  /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>" * "count5<9>" * 
	"count5<10>" * "count5<11>" * "count5<12>" * "count5<13>" * 
	"count5<14>" * "count5<15>" * "count5<16>" * "count5<17>" * 
	"count5<18>" * "count5<19>" * "count5<20>"
    "count5<21>".CLKF  =  fb0
    "count5<21>".PRLD  =  GND    

 "count5<2>".T  =  "count5<21>" * "count5<2>"
	+ /"count5<21>" * "count5<0>" * "count5<1>"
    "count5<2>".CLKF  =  fb0
    "count5<2>".PRLD  =  GND    

 "count5<3>".T  =  "count5<21>" * "count5<3>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>"
    "count5<3>".CLKF  =  fb0
    "count5<3>".PRLD  =  GND    

 "count5<4>".T  =  "count5<21>" * "count5<4>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>"
    "count5<4>".CLKF  =  fb0
    "count5<4>".PRLD  =  GND    

 "count5<5>".T  =  "count5<21>" * "count5<5>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>"
    "count5<5>".CLKF  =  fb0
    "count5<5>".PRLD  =  GND    

 "count5<6>".T  =  "count5<21>" * "count5<6>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>"
    "count5<6>".CLKF  =  fb0
    "count5<6>".PRLD  =  GND    

 "count5<7>".T  =  "count5<21>" * "count5<7>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>"
    "count5<7>".CLKF  =  fb0
    "count5<7>".PRLD  =  GND    

 "count5<8>".T  =  "count5<21>" * "count5<8>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>"
    "count5<8>".CLKF  =  fb0
    "count5<8>".PRLD  =  GND    

 "count5<9>".T  =  "count5<21>" * "count5<9>"
	+ /"count5<21>" * "count5<0>" * "count5<1>" * 
	"count5<2>" * "count5<3>" * "count5<4>" * "count5<5>" * 
	"count5<6>" * "count5<7>" * "count5<8>"
    "count5<9>".CLKF  =  fb0
    "count5<9>".PRLD  =  GND    

 pkled  :=  /pkled
    pkled.CLKF  =  fb0
    pkled.CE =  "count5<21>"
    pkled.PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC95144XL-5-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCC                           
  2 TIE                              74 TIE                           
  3 TIE                              75 TIE                           
  4 fb<5>                            76 TIE                           
  5 TIE                              77 TIE                           
  6 TIE                              78 TIE                           
  7 fb<4>                            79 TIE                           
  8 VCC                              80 TIE                           
  9 fb<3>                            81 TIE                           
 10 fb<2>                            82 TIE                           
 11 fb<1>                            83 TIE                           
 12 fb0                              84 VCC                           
 13 pkled                            85 TIE                           
 14 TIE                              86 TIE                           
 15 TIE                              87 TIE                           
 16 TIE                              88 TIE                           
 17 TIE                              89 GND                           
 18 GND                              90 GND                           
 19 TIE                              91 TIE                           
 20 TIE                              92 TIE                           
 21 TIE                              93 TIE                           
 22 TIE                              94 TIE                           
 23 TIE                              95 TIE                           
 24 TIE                              96 TIE                           
 25 TIE                              97 TIE                           
 26 TIE                              98 TIE                           
 27 TIE                              99 GND                           
 28 TIE                             100 TIE                           
 29 GND                             101 TIE                           
 30 TIE                             102 TIE                           
 31 TIE                             103 TIE                           
 32 lv<8>                           104 TIE                           
 33 lv<11>                          105 TIE                           
 34 lv<9>                           106 TIE                           
 35 TIE                             107 TIE                           
 36 GND                             108 GND                           
 37 VCC                             109 VCC                           
 38 lv<10>                          110 TIE                           
 39 lv<7>                           111 TIE                           
 40 TIE                             112 TIE                           
 41 TIE                             113 TIE                           
 42 VCC                             114 GND                           
 43 TIE                             115 TIE                           
 44 TIE                             116 TIE                           
 45 TIE                             117 TIE                           
 46 TIE                             118 TIE                           
 47 GND                             119 TIE                           
 48 TIE                             120 TIE                           
 49 TIE                             121 TIE                           
 50 TIE                             122 TDO                           
 51 TIE                             123 GND                           
 52 TIE                             124 TIE                           
 53 TIE                             125 TIE                           
 54 TIE                             126 TIE                           
 55 VCC                             127 VCC                           
 56 TIE                             128 TIE                           
 57 TIE                             129 TIE                           
 58 TIE                             130 TIE                           
 59 TIE                             131 TIE                           
 60 TIE                             132 TIE                           
 61 TIE                             133 TIE                           
 62 GND                             134 TIE                           
 63 TDI                             135 TIE                           
 64 TIE                             136 TIE                           
 65 TMS                             137 TIE                           
 66 TIE                             138 TIE                           
 67 TCK                             139 TIE                           
 68 TIE                             140 TIE                           
 69 TIE                             141 VCC                           
 70 TIE                             142 TIE                           
 71 TIE                             143 TIE                           
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC95144XL-5-TQ144
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : OFF
Use Pin Feedback                            : OFF
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : OFF
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 54
