# Reading D:/Modeltech_5.5d/win32/../tcl/vsim/pref.tcl 
# do pack_v1.ldo 
# Model Technology ModelSim SE vcom 5.5d Compiler 2001.09 Aug 22 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity pack_v1
# Model Technology ModelSim SE vcom 5.5d Compiler 2001.09 Aug 22 2001
# -- Loading package standard
# -- Compiling architecture apack_v1 of pack_v1
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity pack_v1
# vsim -t 1ps -L xilinxcorelib pack_v1 
# Loading D:/Modeltech_5.5d/win32/../std.standard
# Loading D:/Modeltech_5.5d/win32/../ieee.std_logic_1164(body)
# Loading D:/Modeltech_5.5d/win32/../ieee.std_logic_arith(body)
# Loading D:/Modeltech_5.5d/win32/../ieee.std_logic_unsigned(body)
# Loading work.pack_v1(apack_v1)
# .wave
# .structure
# .signals
force -freeze sim:/pack_v1/fb0 1 0, 0 {50 ps} -r 100
force -freeze sim:/pack_v1/lclk3 1 0, 0 {50 ps} -r 100
run
