----------------------------------------------------------------
-- FILE : pack_V1.vhd
-- DATE : 05 Apr 2004
-- Last Update : 15 Apr 2004
-- Receives 10MHz clk at FB0
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pack_V1 is
    Port ( FB0   : in std_logic;
	        LCLK3 : in std_logic;
	 		  FB15  : out std_logic;
			  PKLED : out std_logic
           
			 );
end pack_V1;

architecture apack_V1 of pack_V1 is
   

signal clk10, clk20, clk20b : std_logic;
signal count5 : std_logic_vector (21 downto 0):= (others => '0');
signal LED : std_logic := '0';

begin

clk10  <= FB0;
clk20b <= not clk20;
FB15   <= clk20;
PKLED  <= LED;

-------------------------------------------------------------------
-- Divide by 2 of LCLK3 -40 MHz
-------------------------------------------------------------------
p1: process (LCLK3)
  begin  -- process p1
          
    if LCLK3'event and LCLK3 = '1' then  -- rising clock edge
      clk20 <= clk20b;
    end if;
  end process p1;

---------------------------------------------------------------
-- 			5-bit counter
---------------------------------------------------------------	
   process(clk10)
	begin    
      if clk10'event and clk10 = '1' then  -- rising clock edge
        count5 <= count5 + '1';
    --   if count5 = "10011" then
			 if count5(21) = '1' then
	        LED <= not LED;
			  count5 <= (others =>'0');
		  end if;
      end if;
  end process;
---------------------------------------------------------------




end apack_V1;