----------------------------------------------------------------
-- FILE : pack_V1.vhd
-- DATE : 05 Apr 2004
-- Receives 10MHz clk at FB0
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pack_V1 is
    Port ( FB0   : in std_logic;
	 --FB    : in std_logic_vector(24 downto 0);
	        LCLK3 : in std_logic;
	 		  FB15  : out std_logic;
           PKLED : out std_logic
			 );
end pack_V1;

architecture apack_V1 of pack_V1 is
   
signal count5 : std_logic_vector(4 downto 0) := "00000";
signal clk10, PKLEDn, clk20, clk20b: std_logic;
signal LED : std_logic := '1';
   
begin
--	clk10 <= FB0;


--PKLED   <= LED;
clk20b   <= not clk20;
FB15 <= clk20;

---------------------------------------------------------------
-- 			5-bit counter
---------------------------------------------------------------	
   process(clk20)
	begin    
      if clk20'event and clk20 = '1' then  -- rising clock edge
        count5 <= count5 + '1';
--		  if count5 = "10111" then
        if count5 = "10110" then
	        LED <= not LED;
			  count5 <= "00000";
		  end if;
      end if;
  end process;
---------------------------------------------------------------
 
p1: process (LCLK3)
  begin  -- process p1
          
    if LCLK3'event and LCLK3 = '1' then  -- rising clock edge
      clk20 <= clk20b;
    end if;
  end process p1;



end apack_V1;