-- Xilinx Vhdl produced by program ngd2vhdl E.38
-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w pack_v1.nga pack_v1_timesim.vhd 
-- Input file: pack_v1.nga
-- Output file: pack_v1_timesim.vhd
-- Design name: pack_v1
-- Xilinx: C:/Xilinx
-- # of Entities: 1
-- Device: XC95144XL-5-TQ144

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity pack_v1 is
  port (
    pkled : out STD_LOGIC; 
    fb : in STD_LOGIC_VECTOR ( 0 downto 0 ) 
  );
end pack_v1;

architecture Structure of pack_v1 is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal N118 : STD_LOGIC; 
  signal N118_Q : STD_LOGIC; 
  signal N118_D : STD_LOGIC; 
  signal N118_D1 : STD_LOGIC; 
  signal N118_D2_PT_0 : STD_LOGIC; 
  signal N118_D2 : STD_LOGIC; 
  signal count5_0_Q : STD_LOGIC; 
  signal count5_0_D : STD_LOGIC; 
  signal count5_0_CLKF : STD_LOGIC; 
  signal N52 : STD_LOGIC; 
  signal count5_0_CLKF_PT_0 : STD_LOGIC; 
  signal count5_0_D1 : STD_LOGIC; 
  signal count5_0_D2_PT_0 : STD_LOGIC; 
  signal count5_0_D2 : STD_LOGIC; 
  signal count5_1_Q : STD_LOGIC; 
  signal count5_1_D : STD_LOGIC; 
  signal count5_1_CLKF : STD_LOGIC; 
  signal count5_1_CLKF_PT_0 : STD_LOGIC; 
  signal count5_1_D1 : STD_LOGIC; 
  signal count5_1_D2_PT_0 : STD_LOGIC; 
  signal count5_1_D2 : STD_LOGIC; 
  signal count5_1_D_TFF : STD_LOGIC; 
  signal count5_2_Q : STD_LOGIC; 
  signal count5_2_D : STD_LOGIC; 
  signal count5_2_CLKF : STD_LOGIC; 
  signal count5_2_CLKF_PT_0 : STD_LOGIC; 
  signal count5_2_D1 : STD_LOGIC; 
  signal count5_2_D2_PT_0 : STD_LOGIC; 
  signal count5_2_D2 : STD_LOGIC; 
  signal count5_2_D_TFF : STD_LOGIC; 
  signal count5_3_Q : STD_LOGIC; 
  signal count5_3_D : STD_LOGIC; 
  signal count5_3_CLKF : STD_LOGIC; 
  signal count5_3_CLKF_PT_0 : STD_LOGIC; 
  signal count5_3_D1 : STD_LOGIC; 
  signal count5_3_D2_PT_0 : STD_LOGIC; 
  signal count5_3_D2 : STD_LOGIC; 
  signal count5_3_D_TFF : STD_LOGIC; 
  signal count5_4_Q : STD_LOGIC; 
  signal count5_4_D : STD_LOGIC; 
  signal count5_4_CLKF : STD_LOGIC; 
  signal count5_4_CLKF_PT_0 : STD_LOGIC; 
  signal count5_4_D1 : STD_LOGIC; 
  signal count5_4_D2_PT_0 : STD_LOGIC; 
  signal count5_4_D2 : STD_LOGIC; 
  signal count5_4_D_TFF : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_N118_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N118_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count5_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count5_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal count5 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
begin
  pkled_0 : X_BUF
    port map (
      I => N118,
      O => pkled
    );
  N118_1 : X_BUF
    port map (
      I => N118_Q,
      O => N118
    );
  N118_REG : X_BUF
    port map (
      I => N118_D,
      O => N118_Q
    );
  GND_ZERO : X_ZERO
    port map (
      O => GND
    );
  N118_D1_2 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N118_D1
    );
  N118_D2_PT_0_3 : X_AND5
    port map (
      I0 => NlwInverterSignal_N118_D2_PT_0_IN0,
      I1 => count5(1),
      I2 => count5(2),
      I3 => NlwInverterSignal_N118_D2_PT_0_IN3,
      I4 => count5(4),
      O => N118_D2_PT_0
    );
  N118_D2_4 : X_OR2
    port map (
      I0 => N118_D2_PT_0,
      I1 => N118_D2_PT_0,
      O => N118_D2
    );
  N118_XOR : X_XOR2
    port map (
      I0 => N118_D1,
      I1 => N118_D2,
      O => N118_D
    );
  count5_0_Q_5 : X_BUF
    port map (
      I => count5_0_Q,
      O => count5(0)
    );
  count5_0_REG : X_FF
    port map (
      I => count5_0_D,
      CE => VCC,
      CLK => count5_0_CLKF,
      SET => GND,
      RST => PRLD,
      O => count5_0_Q
    );
  VCC_ONE : X_ONE
    port map (
      O => VCC
    );
  count5_0_CLKF_PT_0_6 : X_AND2
    port map (
      I0 => N52,
      I1 => N52,
      O => count5_0_CLKF_PT_0
    );
  count5_0_CLKF_7 : X_OR2
    port map (
      I0 => count5_0_CLKF_PT_0,
      I1 => count5_0_CLKF_PT_0,
      O => count5_0_CLKF
    );
  count5_0_D1_8 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => count5_0_D1
    );
  count5_0_D2_PT_0_9 : X_AND2
    port map (
      I0 => NlwInverterSignal_count5_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_count5_0_D2_PT_0_IN1,
      O => count5_0_D2_PT_0
    );
  count5_0_D2_10 : X_OR2
    port map (
      I0 => count5_0_D2_PT_0,
      I1 => count5_0_D2_PT_0,
      O => count5_0_D2
    );
  count5_0_XOR : X_XOR2
    port map (
      I0 => count5_0_D1,
      I1 => count5_0_D2,
      O => count5_0_D
    );
  N52_11 : X_BUF
    port map (
      I => fb(0),
      O => N52
    );
  count5_1_Q_12 : X_BUF
    port map (
      I => count5_1_Q,
      O => count5(1)
    );
  count5_1_REG : X_FF
    port map (
      I => count5_1_D,
      CE => VCC,
      CLK => count5_1_CLKF,
      SET => GND,
      RST => PRLD,
      O => count5_1_Q
    );
  count5_1_CLKF_PT_0_13 : X_AND2
    port map (
      I0 => N52,
      I1 => N52,
      O => count5_1_CLKF_PT_0
    );
  count5_1_CLKF_14 : X_OR2
    port map (
      I0 => count5_1_CLKF_PT_0,
      I1 => count5_1_CLKF_PT_0,
      O => count5_1_CLKF
    );
  count5_1_D1_15 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => count5_1_D1
    );
  count5_1_D2_PT_0_16 : X_AND2
    port map (
      I0 => count5(0),
      I1 => count5(0),
      O => count5_1_D2_PT_0
    );
  count5_1_D2_17 : X_OR2
    port map (
      I0 => count5_1_D2_PT_0,
      I1 => count5_1_D2_PT_0,
      O => count5_1_D2
    );
  count5_1_D_18 : X_XOR2
    port map (
      I0 => count5_1_D_TFF,
      I1 => count5_1_Q,
      O => count5_1_D
    );
  count5_1_XOR : X_XOR2
    port map (
      I0 => count5_1_D1,
      I1 => count5_1_D2,
      O => count5_1_D_TFF
    );
  count5_2_Q_19 : X_BUF
    port map (
      I => count5_2_Q,
      O => count5(2)
    );
  count5_2_REG : X_FF
    port map (
      I => count5_2_D,
      CE => VCC,
      CLK => count5_2_CLKF,
      SET => GND,
      RST => PRLD,
      O => count5_2_Q
    );
  count5_2_CLKF_PT_0_20 : X_AND2
    port map (
      I0 => N52,
      I1 => N52,
      O => count5_2_CLKF_PT_0
    );
  count5_2_CLKF_21 : X_OR2
    port map (
      I0 => count5_2_CLKF_PT_0,
      I1 => count5_2_CLKF_PT_0,
      O => count5_2_CLKF
    );
  count5_2_D1_22 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => count5_2_D1
    );
  count5_2_D2_PT_0_23 : X_AND2
    port map (
      I0 => count5(0),
      I1 => count5(1),
      O => count5_2_D2_PT_0
    );
  count5_2_D2_24 : X_OR2
    port map (
      I0 => count5_2_D2_PT_0,
      I1 => count5_2_D2_PT_0,
      O => count5_2_D2
    );
  count5_2_D_25 : X_XOR2
    port map (
      I0 => count5_2_D_TFF,
      I1 => count5_2_Q,
      O => count5_2_D
    );
  count5_2_XOR : X_XOR2
    port map (
      I0 => count5_2_D1,
      I1 => count5_2_D2,
      O => count5_2_D_TFF
    );
  count5_3_Q_26 : X_BUF
    port map (
      I => count5_3_Q,
      O => count5(3)
    );
  count5_3_REG : X_FF
    port map (
      I => count5_3_D,
      CE => VCC,
      CLK => count5_3_CLKF,
      SET => GND,
      RST => PRLD,
      O => count5_3_Q
    );
  count5_3_CLKF_PT_0_27 : X_AND2
    port map (
      I0 => N52,
      I1 => N52,
      O => count5_3_CLKF_PT_0
    );
  count5_3_CLKF_28 : X_OR2
    port map (
      I0 => count5_3_CLKF_PT_0,
      I1 => count5_3_CLKF_PT_0,
      O => count5_3_CLKF
    );
  count5_3_D1_29 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => count5_3_D1
    );
  count5_3_D2_PT_0_30 : X_AND3
    port map (
      I0 => count5(0),
      I1 => count5(1),
      I2 => count5(2),
      O => count5_3_D2_PT_0
    );
  count5_3_D2_31 : X_OR2
    port map (
      I0 => count5_3_D2_PT_0,
      I1 => count5_3_D2_PT_0,
      O => count5_3_D2
    );
  count5_3_D_32 : X_XOR2
    port map (
      I0 => count5_3_D_TFF,
      I1 => count5_3_Q,
      O => count5_3_D
    );
  count5_3_XOR : X_XOR2
    port map (
      I0 => count5_3_D1,
      I1 => count5_3_D2,
      O => count5_3_D_TFF
    );
  count5_4_Q_33 : X_BUF
    port map (
      I => count5_4_Q,
      O => count5(4)
    );
  count5_4_REG : X_FF
    port map (
      I => count5_4_D,
      CE => VCC,
      CLK => count5_4_CLKF,
      SET => GND,
      RST => PRLD,
      O => count5_4_Q
    );
  count5_4_CLKF_PT_0_34 : X_AND2
    port map (
      I0 => N52,
      I1 => N52,
      O => count5_4_CLKF_PT_0
    );
  count5_4_CLKF_35 : X_OR2
    port map (
      I0 => count5_4_CLKF_PT_0,
      I1 => count5_4_CLKF_PT_0,
      O => count5_4_CLKF
    );
  count5_4_D1_36 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => count5_4_D1
    );
  count5_4_D2_PT_0_37 : X_AND4
    port map (
      I0 => count5(0),
      I1 => count5(1),
      I2 => count5(2),
      I3 => count5(3),
      O => count5_4_D2_PT_0
    );
  count5_4_D2_38 : X_OR2
    port map (
      I0 => count5_4_D2_PT_0,
      I1 => count5_4_D2_PT_0,
      O => count5_4_D2
    );
  count5_4_D_39 : X_XOR2
    port map (
      I0 => count5_4_D_TFF,
      I1 => count5_4_Q,
      O => count5_4_D
    );
  count5_4_XOR : X_XOR2
    port map (
      I0 => count5_4_D1,
      I1 => count5_4_D2,
      O => count5_4_D_TFF
    );
  NlwInverterBlock_N118_D2_PT_0_IN0 : X_INV
    port map (
      I => count5(0),
      O => NlwInverterSignal_N118_D2_PT_0_IN0
    );
  NlwInverterBlock_N118_D2_PT_0_IN3 : X_INV
    port map (
      I => count5(3),
      O => NlwInverterSignal_N118_D2_PT_0_IN3
    );
  NlwInverterBlock_count5_0_D2_PT_0_IN0 : X_INV
    port map (
      I => count5(0),
      O => NlwInverterSignal_count5_0_D2_PT_0_IN0
    );
  NlwInverterBlock_count5_0_D2_PT_0_IN1 : X_INV
    port map (
      I => count5(0),
      O => NlwInverterSignal_count5_0_D2_PT_0_IN1
    );
  NlwBlockROC : ROC generic map ( WIDTH => 100 ns)
     port map (O => PRLD);
end Structure;