Design of a PCI DAS

This poster depicts the design and development of a PCI-based Data Acquisition Sytem (DAS). The motivation behind this work, features of the system, overview of the design, example applications, block diagram, and also some details about major components used in the design are explained.

Motivation

Considering the data acquisition system requirements for different projects , we realized the benefits of developing a PCI-based DAS with features that would be a superset of most of the existing DAS (like the AMCC, PLX-V1, V2, ISA cards) and have more functionality for real-time data processing and high-speed data acquisition. Although the design is optimized considering the needs of a few major applications like the 12m backend, new backend for the ORT and, for a phased replacement of the exsiting high-speed data acquisition systems, it would also serve as a standard DAS for various other projects.

Design Overview

The PCI interface is achieved using a PCI9054 chip. An FPGA (PROCESS-FPGA) handles the real-time data processing. The high-speed data transaction across the PCI bus is handled by another FPGA (TRANSACT-FPGA). The logic for mininum address decoding and FPGA configuration is provided by a CPLD (CONFIG-CPLD). The external inputs/outputs to the system are arranged and multiplexed through another CPLD (PACK-CPLD). The inputs to the DAS could be from the high-speed parallel LVDS, Serial LVDS or RS-422 paths. Few parallel LVDS, Serial LVDS and RS422 outputs are also provided. Onboard RAM connected to the PROCESS-FPGA serves as a temporary data storage area.

Team/Authors:

Kamini P. A., Girish B. S., Prabu T

Udayashankar B. K., Srivani K. S.

Special Acknowledgements to C. R. Subrahmanya for his timely suggestions and guidance. Special thanks to N. UdayaShankar and A. Krishnan for their interest in the project. Acknowledgements to C. Vinutha and other colleagues in the Lab.