AGFO_FIBRE_SX_V3AA Project Status
Project File: agfo_fibre_sx_v3aa.ise Current State: Programming File Not Generated
Module Name: AGFO_FIBRE_V3a_LX
  • Errors:
No Errors
Target Device: xc5vlx50t-1ff665
  • Warnings:
3475 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Tue Apr 28 12:09:34 2009
 
AGFO_FIBRE_SX_V3AA Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 5,405 28,800 18%  
    Number used as Flip Flops 5,405      
Number of Slice LUTs 3,268 28,800 11%  
    Number used as logic 2,977 28,800 10%  
        Number using O6 output only 2,672      
        Number using O5 output only 226      
        Number using O5 and O6 79      
    Number used as Memory 276 7,680 3%  
        Number used as Shift Register 276      
            Number using O6 output only 276      
    Number used as exclusive route-thru 15      
Number of route-thrus 279 57,600 1%  
    Number using O6 output only 241      
    Number using O5 output only 38      
Slice Logic Distribution     
Number of occupied Slices 2,113 7,200 29%  
Number of LUT Flip Flop pairs used 6,576      
    Number with an unused Flip Flop 1,171 6,576 17%  
    Number with an unused LUT 3,308 6,576 50%  
    Number of fully used LUT-FF pairs 2,097 6,576 31%  
    Number of unique control sets 410      
IO Utilization     
Number of bonded IOBs 90 360 25%  
    IOB Flip Flops 1      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 31 60 51%  
    Number using BlockRAM only 31      
Total primitives used     
        Number of 36k BlockRAM used 21      
        Number of 18k BlockRAM used 20      
Total Memory used (KB) 1,116 2,160 51%  
Number of BUFG/BUFGCTRLs 24 32 75%  
    Number used as BUFGs 24      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 6 12 50%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 4,205,674      
Additional JTAG gate count for IOBs 5,280      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 28 11:31:46 200903462 Warnings135 Infos
Translation ReportCurrentTue Apr 28 11:32:08 200901 Warning4 Infos
Map ReportCurrentTue Apr 28 11:38:00 200904 Warnings12 Infos
Place and Route ReportCurrentTue Apr 28 11:39:29 200903 Warnings2 Infos
Static Timing ReportCurrentTue Apr 28 11:40:00 2009002 Infos
Bitgen ReportCurrentTue Apr 28 11:41:53 200905 Warnings1 Info