AGFO_FIBRE_V6CP2_SX Project Status
Project File: agfo_fibre_V6cp2_SX.ise Current State: Programming File Generated
Module Name: AGFO_FIBRE_V6c_SX
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
5671 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Wed Nov 4 11:32:19 2009
 
AGFO_FIBRE_V6CP2_SX Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 5,246 32,640 16%  
    Number used as Flip Flops 5,246      
Number of Slice LUTs 4,851 32,640 14%  
    Number used as logic 4,415 32,640 13%  
        Number using O6 output only 3,985      
        Number using O5 output only 208      
        Number using O5 and O6 222      
    Number used as Memory 422 12,480 3%  
        Number used as Shift Register 422      
            Number using O6 output only 422      
    Number used as exclusive route-thru 14      
Number of route-thrus 240 65,280 1%  
    Number using O6 output only 222      
    Number using O5 output only 18      
Slice Logic Distribution     
Number of occupied Slices 2,479 8,160 30%  
Number of LUT Flip Flop pairs used 7,347      
    Number with an unused Flip Flop 2,101 7,347 28%  
    Number with an unused LUT 2,496 7,347 33%  
    Number of fully used LUT-FF pairs 2,750 7,347 37%  
    Number of unique control sets 491      
IO Utilization     
Number of bonded IOBs 180 360 50%  
    IOB Flip Flops 62      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 31 132 23%  
    Number using BlockRAM only 31      
Total primitives used     
        Number of 36k BlockRAM used 21      
        Number of 18k BlockRAM used 20      
Total Memory used (KB) 1,116 4,752 23%  
Number of BUFG/BUFGCTRLs 21 32 65%  
    Number used as BUFGs 21      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 2 12 16%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 4,207,273      
Additional JTAG gate count for IOBs 9,600      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Sep 29 17:16:01 200905652 Warnings113 Infos
Translation ReportCurrentTue Sep 29 17:16:13 200904 Warnings6 Infos
Map ReportCurrentTue Sep 29 17:19:06 200909 Warnings12 Infos
Place and Route ReportCurrentTue Sep 29 17:19:57 200903 Warnings2 Infos
Static Timing ReportCurrentTue Sep 29 17:20:15 2009002 Infos
Bitgen ReportCurrentTue Sep 29 17:21:26 200903 Warnings1 Info