X14_AGFO_V6CP3_SX Project Status
Project File: X14_AgFo_V6cp3_SX.ise Current State: Programming File Generated
Module Name: AGFO_FIBRE_V6cp3_SX
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
5749 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Thu Aug 5 16:54:08 2010
 
X14_AGFO_V6CP3_SX Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 5,638 32,640 17%  
    Number used as Flip Flops 5,638      
Number of Slice LUTs 5,424 32,640 16%  
    Number used as logic 4,970 32,640 15%  
        Number using O6 output only 4,525      
        Number using O5 output only 222      
        Number using O5 and O6 223      
    Number used as Memory 420 12,480 3%  
        Number used as Shift Register 420      
            Number using O6 output only 420      
    Number used as exclusive route-thru 34      
Number of route-thrus 295 65,280 1%  
    Number using O6 output only 236      
    Number using O5 output only 39      
    Number using O5 and O6 20      
Slice Logic Distribution     
Number of occupied Slices 2,268 8,160 27%  
Number of LUT Flip Flop pairs used 7,571      
    Number with an unused Flip Flop 1,933 7,571 25%  
    Number with an unused LUT 2,147 7,571 28%  
    Number of fully used LUT-FF pairs 3,491 7,571 46%  
    Number of unique control sets 513      
IO Utilization     
Number of bonded IOBs 180 360 50%  
    IOB Flip Flops 62      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 32 132 24%  
    Number using BlockRAM only 32      
Total primitives used     
        Number of 36k BlockRAM used 21      
        Number of 18k BlockRAM used 21      
Total Memory used (KB) 1,134 4,752 23%  
Number of BUFG/BUFGCTRLs 21 32 65%  
    Number used as BUFGs 21      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 2 12 16%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 4,279,573      
Additional JTAG gate count for IOBs 9,600      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Apr 21 07:21:32 201005730 Warnings121 Infos
Translation ReportCurrentWed Apr 21 07:21:48 201004 Warnings6 Infos
Map ReportCurrentWed Apr 21 07:25:08 201009 Warnings12 Infos
Place and Route ReportCurrentWed Apr 21 07:26:04 201003 Warnings2 Infos
Static Timing ReportCurrentWed Apr 21 07:26:22 2010002 Infos
Bitgen ReportCurrentWed Apr 21 07:27:31 201003 Warnings1 Info