X14_AGFO_V6CP3_SX Project Status
Project File: X14_AgFo_V6cp3_SX.ise Current State: Programming File Generated
Module Name: X14_AgFo_V6cp3_SX
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
5813 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Thu Dec 9 04:34:49 2010
 
X14_AGFO_V6CP3_SX Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 5,638 32,640 17%  
    Number used as Flip Flops 5,638      
Number of Slice LUTs 5,426 32,640 16%  
    Number used as logic 4,971 32,640 15%  
        Number using O6 output only 4,525      
        Number using O5 output only 222      
        Number using O5 and O6 224      
    Number used as Memory 420 12,480 3%  
        Number used as Shift Register 420      
            Number using O6 output only 420      
    Number used as exclusive route-thru 35      
Number of route-thrus 311 65,280 1%  
    Number using O6 output only 236      
    Number using O5 output only 54      
    Number using O5 and O6 21      
Slice Logic Distribution     
Number of occupied Slices 2,022 8,160 24%  
Number of LUT Flip Flop pairs used 7,100      
    Number with an unused Flip Flop 1,462 7,100 20%  
    Number with an unused LUT 1,674 7,100 23%  
    Number of fully used LUT-FF pairs 3,964 7,100 55%  
    Number of unique control sets 513      
IO Utilization     
Number of bonded IOBs 183 360 50%  
    IOB Flip Flops 62      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 32 132 24%  
    Number using BlockRAM only 32      
Total primitives used     
        Number of 36k BlockRAM used 21      
        Number of 18k BlockRAM used 21      
Total Memory used (KB) 1,134 4,752 23%  
Number of BUFG/BUFGCTRLs 21 32 65%  
    Number used as BUFGs 21      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 2 12 16%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 4,279,615      
Additional JTAG gate count for IOBs 9,744      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Aug 5 17:15:15 201005794 Warnings121 Infos
Translation ReportCurrentThu Aug 5 17:18:00 201004 Warnings6 Infos
Map ReportCurrentThu Aug 5 17:21:37 201009 Warnings12 Infos
Place and Route ReportCurrentThu Aug 5 17:22:32 201003 Warnings2 Infos
Static Timing ReportCurrentThu Aug 5 17:22:49 2010002 Infos
Bitgen ReportCurrentThu Aug 5 17:23:58 201003 Warnings1 Info