AGFO12_B5 Project Status
Project File: agfo12_b5.ise Current State: Programming File Not Generated
Module Name: agfo12_b4
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
1484 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Mon Feb 16 11:57:12 2009
 
AGFO12_B5 Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,376 32,640 10%  
    Number used as Flip Flops 3,376      
Number of Slice LUTs 4,452 32,640 13%  
    Number used as logic 4,379 32,640 13%  
        Number using O6 output only 3,967      
        Number using O5 output only 373      
        Number using O5 and O6 39      
    Number used as Memory 31 12,480 1%  
        Number used as Shift Register 31      
            Number using O6 output only 31      
    Number used as exclusive route-thru 42      
Number of route-thrus 426 65,280 1%  
    Number using O6 output only 415      
    Number using O5 output only 11      
Slice Logic Distribution     
Number of occupied Slices 2,021 8,160 24%  
Number of LUT Flip Flop pairs used 5,487      
    Number with an unused Flip Flop 2,111 5,487 38%  
    Number with an unused LUT 1,035 5,487 18%  
    Number of fully used LUT-FF pairs 2,341 5,487 42%  
    Number of unique control sets 385      
IO Utilization     
Number of bonded IOBs 99 360 27%  
    IOB Flip Flops 8      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 23 132 17%  
    Number using BlockRAM only 20      
    Number using FIFO only 3      
Total primitives used     
        Number of 18k BlockRAM used 37      
        Number of 18k FIFO used 3      
Total Memory used (KB) 720 4,752 15%  
Number of BUFG/BUFGCTRLs 31 32 96%  
    Number used as BUFGs 31      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 6 12 50%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Number of SYSMONs 1 1 100%  
Total equivalent gate count for design 2,725,761      
Additional JTAG gate count for IOBs 5,712      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 16 17:48:25 200801390 Warnings278 Infos
Translation ReportCurrentTue Dec 16 17:48:44 2008004 Infos
Map ReportCurrentTue Dec 16 17:52:54 2008088 Warnings12 Infos
Place and Route ReportCurrentTue Dec 16 17:54:02 200803 Warnings2 Infos
Static Timing ReportCurrentTue Dec 16 17:54:25 2008002 Infos
Bitgen ReportCurrentTue Dec 16 17:55:49 200803 Warnings1 Info