onerror {resume}
quietly WaveActivateNextPane {} 0
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv1_p & lv2_p & lv3_p & lv4_p & lv5_p & lv6_p & lv7_p & lv8_p & lv9_p & lv10_p )} dasop
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv1_p & lv2_p & lv3_p & lv4_p & lv5_p & lv6_p & lv7_p & lv8_p & lv9_p & lv10_p )} dasop
quietly virtual signal -install /tb_v4_sx_vhd/uut { /tb_v4_sx_vhd/uut/data_out_f1(9 downto 0)} depack
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv10_p & lv9_p & lv8_p & lv7_p & lv6_p & lv5_p & lv4_p & lv3_p & lv2_p & lv1_p )} DASOP1
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv10_p & lv9_p & lv8_p & lv7_p & lv6_p & lv5_p & lv4_p & lv3_p & lv2_p & lv1_p )} DASOP1
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv1_p & lv2_p & lv3_p & lv4_p & lv5_p & lv6_p & lv7_p & lv8_p & lv9_p & lv10_p )} dasop
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv1_p & lv2_p & lv3_p & lv4_p & lv5_p & lv6_p & lv7_p & lv8_p & lv9_p & lv10_p )} dasop
quietly virtual signal -install /tb_v4_sx_vhd/uut { /tb_v4_sx_vhd/uut/data_out_f1(9 downto 0)} depack
quietly virtual signal -install /tb_v4_sx_vhd/uut { (context /tb_v4_sx_vhd/uut )(lv10_p & lv9_p & lv8_p & lv7_p & lv6_p & lv5_p & lv4_p & lv3_p & lv2_p & lv1_p )} DASOP1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/an
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dn
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/gc8_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/gc8_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/extck2_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/extck2_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv1_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv2_n
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv1_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv10_p
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/dasop
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv9_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv8_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv7_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv6_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv5_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv4_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv3_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv2_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv1_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv3_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv4_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv5_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv6_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv7_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv8_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv9_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv10_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv11_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv11_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv65_p
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/dasop
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv12_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv12_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv65_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtck3_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtck3_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkp_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkn_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkp_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkn_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv67_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv67_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv69_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv69_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig16
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/deser_command
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/delay_ce
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/delay_inc_dec
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_command
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/din
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/led_cnt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/vsib_pvalid
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/vsib_trigger
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_mode
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ch_sel_mode
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_rd_er_flag
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1d_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2d_p2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/vsib_data
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_l1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_delayed
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_rd_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds1_1a_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fdb2_1b_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds3_1c_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds6_2b_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fda7_2c_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck4_1d_clk2bufg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck5_2a_clk2bufg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck8_2d_clk2bufg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1d_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2d_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_load_delay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_reset_chno
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fout_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_clk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/chip_sel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/read_reg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/read_start
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/read_started
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_rdclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_synch
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds1_1a_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fdb2_1b_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds3_1c_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds6_2b_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fda7_2c_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck3_1c_clk2bufg
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out16
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dinl1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regcebl1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/chsel_opreg_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/a1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/b1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/c1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/d1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/a2_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/b2_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/c2_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/d2_clk
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_a1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_b1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_c1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_d1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_a2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_b2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_c2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_d2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_a1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_b1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_c1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_d1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_a2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_b2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_c2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_d2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ndata_ready_mux_c1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk200
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lrst1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/delay_ce_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/channel_selected
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/channel_no
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usbl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/check_ld_low
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_load_int
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_load
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ch_sel_reg
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ch_sel_reg1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_to_vsib
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_to_vsib
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fibre_bkpln_sel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/vsib_fibre_num
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_of_chns_to_vsib
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/den_cnt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/busy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/drdy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/eos
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/den
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/alm
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/channel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/daddr
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/do
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_plllkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_plllkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_clkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_clkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_rxclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_rxclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_rxclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_rxclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/system_reset
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rxn_in_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rxp_in_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txn_out_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txp_out_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtreset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wrclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk_125
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wrclk_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wrclk1_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdclk_sig
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_refclk_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_refclk_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_txusrclk20_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_txusrclk20_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0rx_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0rx_rst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1rx_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1rx_rst1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/fibre_no
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tx_reset
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/counter_data
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/ram_data1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f1
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/depack
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/data_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv11_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv65_p
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/DASOP1
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(9)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(8)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(7)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(6)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(5)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(4)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(3)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(2)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(1)
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1(0)
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en16
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_enable
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_to_vsib
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/global_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/refclkout_pll2_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/refclkout_pll5_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm0_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm3_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm1_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm4_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk125_mgt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lock_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lock_out1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lock_out2
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/reset_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/lock_out1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/lock_out2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk30
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk163
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkdv
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkfb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkfx
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk163_int
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkdv1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk0a
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkfb1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkfx1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkdv2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clk0b
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkfb2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_clock_gen/clkfx2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk125mhz
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fout_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/valid_enable
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/counter_enable
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/counter_data
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/trans_test/c1
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/trans_test/c2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/fout
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/actual_diag
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/addra
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/addrb1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/addrb2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/addrb3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/addrb4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/c1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/charisk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/charisk2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/charisk3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/charisk4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/clk_165
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/counter_regceb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/counter_regceb_int
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/data_load
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/dout1
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/dout2
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/dout3
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/dout4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/enb1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/enb2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/enb3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/enb4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/fibre_no
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/ip_dpram_en
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/no_ch_fibre1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/no_ch_fibre2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/no_ch_fibre3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/no_ch_fibre4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/no_ch_fibre_cnt_out
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/valid_datal2
add wave -noupdate -format Literal -expand /tb_v4_sx_vhd/uut/trans_test/wr_en1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/wr_en2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/wr_en3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/wr_en4
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/ram_data1
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/ram_data2
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/ram_data3
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/trans_test/ram_data4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rd_complete
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rd_complete1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rd_complete2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rd_complete3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rd_complete4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/rst_latched
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/sctn_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/sctn_l1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/start_rd1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/start_rd2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/start_rd3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/start_rd4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/tile0_txusrclk20
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/tile0tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/tile1_txusrclk20
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/tile1tx_rst
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/valid_data
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/trans_test/valid_datal1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/trans_test/valid_regceb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclk_pad_n_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclk_pad_p_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_refclk_pad_n_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_refclk_pad_p_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/gtpreset_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_plllkdet_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_plllkdet_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_clkdet_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_clkdet_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/gtp_system_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxclk0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxclk1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxclk0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxclk1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxdata0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxdata1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxdata0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxdata1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rxn_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rxp_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/txn_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/txp_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcharisk0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcharisk1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcharisk0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcharisk1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclk_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_refclk_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0rx_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0rx_rst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1rx_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1rx_rst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txusrclk20_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txusrclk20_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/refclkout_pll2_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/refclkout_pll5_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm0_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm3_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm1_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm4_locked_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_in0_r
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_in1_r
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone0_r
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone0_r2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone1_r
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone1_r2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_resetdone0_r
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_resetdone0_r2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_resetdone1_r
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_resetdone1_r2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_loopback0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_loopback1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxpowerdown0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxpowerdown1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txpowerdown0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txpowerdown1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchariscomma0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchariscomma1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxdisperr0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxdisperr1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxnotintable0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxnotintable1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchanbondseq0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchanbondseq1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenchansync0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenchansync1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxclkcorcnt0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxclkcorcnt1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyteisaligned0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyteisaligned1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyterealign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyterealign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcommadet0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcommadet1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenmcommaalign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenmcommaalign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenpcommaalign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenpcommaalign1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxrecclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxrecclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcdrreset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcdrreset1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbufstatus0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbufstatus1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchanisaligned0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchanisaligned1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchanrealign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxchanrealign1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxlossofsync0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxlossofsync1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_gtpreset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_plllkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclkout_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txcharisk0_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txcharisk1_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txdata0_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txdata1_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_loopback0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_loopback1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxpowerdown0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxpowerdown1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txpowerdown0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txpowerdown1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchariscomma0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchariscomma1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxdisperr0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxdisperr1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxnotintable0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxnotintable1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcharisk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchanbondseq0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchanbondseq1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxenchansync0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxenchansync1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxclkcorcnt0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxclkcorcnt1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxbyteisaligned0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxbyteisaligned1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxbyterealign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxbyterealign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcommadet0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcommadet1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxenmcommaalign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxenmcommaalign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxenpcommaalign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxenpcommaalign1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxrecclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxrecclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcdrreset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxcdrreset1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxbufstatus0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxbufstatus1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchanisaligned0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchanisaligned1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchanrealign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxchanrealign1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxlossofsync0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxlossofsync1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_gtpreset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_plllkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_refclkout_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_resetdone0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_resetdone1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txcharisk0_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txcharisk1_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txdata0_ii
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txdata1_ii
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_system_reset_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_system_reset0_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxreset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txreset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_system_reset1_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxreset1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txreset1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_system_reset0_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxreset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txreset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_system_reset1_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxreset1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txreset1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tied_to_ground_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tied_to_ground_vec_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tied_to_vcc_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tied_to_vcc_vec_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/drp_clk_in_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/txpmasetphase_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/txenpmaphasealign_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclkout_bufg_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxusrclk20_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txusrclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txusrclk20_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxusrclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txusrclk20_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxusrclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxusrclk21_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxusrclk20_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxusrclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxusrclk21_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxusrclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txusrclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm0_locked_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm0_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxrecclk0_to_dcm_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm1_locked_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm1_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxrecclk0_to_dcm_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/refclkout_pll2_locked_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/refclkout_pll2_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_refclkout_to_cmt_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm3_locked_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm3_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxrecclk1_to_dcm_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm4_locked_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rxrecclk_dcm4_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rxrecclk1_to_dcm_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/refclkout_pll5_locked_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/refclkout_pll5_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclkout_to_cmt_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_refclk_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_matchn0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txcharisk0_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txdata0_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_error_count0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_frame_check0_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_inc_in0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_inc_out0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_matchn1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txcharisk1_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_txdata1_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_error_count1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_frame_check1_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_inc_in1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_inc_out1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_refclk_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_matchn0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txcharisk0_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txdata0_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_error_count0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_frame_check0_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_inc_in0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_inc_out0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_matchn1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txcharisk1_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_txdata1_float_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_error_count1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_frame_check1_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_inc_in1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_inc_out1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/reset_on_data_error_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_sync_done0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_reset_rxsync0_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_sync_done1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_reset_rxsync1_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_sync_done0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_reset_rxsync0_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_sync_done1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_reset_rxsync1_c
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_sync_done_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/reset_txsync_c
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/shared_vio_control_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_data_vio_control0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rx_data_vio_control0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_control0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_data_vio_control1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rx_data_vio_control1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_control1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/shared_vio_in_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/shared_vio_out_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_data_vio_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_data_vio_out0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_data_vio_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tx_data_vio_out1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rx_data_vio_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rx_data_vio_out0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rx_data_vio_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rx_data_vio_out1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_tx_data_vio_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_tx_data_vio_out0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_data_vio_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_data_vio_out0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_ila_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_tx_data_vio_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_tx_data_vio_out1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_data_vio_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rx_data_vio_out1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_ila_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_tx_data_vio_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_tx_data_vio_out0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_data_vio_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_data_vio_out0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_ila_in0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_tx_data_vio_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_tx_data_vio_out1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_data_vio_in1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_rx_data_vio_out1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_ila_in1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/gtpreset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/mux_sel_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/user_tx_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/user_rx_reset_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_clk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_clk_mux_out0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_clk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/ila_clk_mux_out1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/wr_en2_out_sig
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/cnt
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_cnt
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_cnt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_tmp_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_tmp_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_tmp1_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_tmp1_rst
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_cnt0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_cnt1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0rx_tmp_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0rx_tmp_rst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0rx_tmp1_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0rx_tmp1_rst1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_cnt0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1_cnt1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1rx_tmp_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1rx_tmp_rst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1rx_tmp1_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile1rx_tmp1_rst1
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/charisk
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/checksum
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/checksum_int
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/chk_flag
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/chsel_cnt
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/chselreg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/clk_125
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/clk_165
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/countera
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/counterb
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/packrx1/data_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/data_inl1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/data_inl2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/data_latched
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/data_latched_125
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/packrx1/data_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/data_ready
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/data_ready_165
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/header1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/header2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/header3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/last_valid_data_125
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/last_valid_data_165
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/lrst
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/packrx1/node_seq_reg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/regceb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/regceb_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/rst_125
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/rst_latched
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/rx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/valid_data
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/valid_datal
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/valid_datal1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/valid_datal2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/packrx1/valid_datal3
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/burst_mode
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/burst_mode_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/burst_rd_complete_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/burst_rd_completel1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/ch_sel_mode
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/ch_sel_mode_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/ch_sel_reg
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/channel_no
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/check_ld_low
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/data_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/data_read
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/delay_counter
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/data_out_f1
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/dinl1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/dinl1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/dinl1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/dinl2_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/empty
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/fifo_rd_addrs_inc
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/fifo_rd_er_flag_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/first_marker
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/fout_counter
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/fout_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/foutl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/last_data
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/marker
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/marker_count
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/marker_rd_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/marker_read
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/mux1_local
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/data_out
add wave -noupdate -format Literal -radix binary /tb_v4_sx_vhd/uut/op_fifo_inst1/mux_cnt3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_trigger
add wave -noupdate -format Literal -radix binary /tb_v4_sx_vhd/uut/op_fifo_inst1/mux_cnt3l1
add wave -noupdate -format Literal -radix binary /tb_v4_sx_vhd/uut/op_fifo_inst1/mux_cnt3l2
add wave -noupdate -format Literal -radix binary /tb_v4_sx_vhd/uut/op_fifo_inst1/mux_cnt3l3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/rd_adrs_flag
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/rd_clk_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/rd_data_count
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/rd_en
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/read_counter
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/read_start_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/read_started
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/read_started_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regceb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regceb_clk_ratio
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regceb_cnt
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/regceb_counter
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regceb_flag
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regceb_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regcebl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regcebl1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/regcebl2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/reset_rd_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/rst_opreg_load
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/sctn_counter
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/sctn_flag
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/sctn_flag_rd_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/sctn_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/sctnl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/start_read
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/op_fifo_inst1/trigger_counter
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/usb_load_int
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/usbl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/valid_data
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/mux1_out
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/op_fifo_inst1/data_out
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/vsib_data
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/DASOP1
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv10_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv9_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv8_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv7_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv6_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv5_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv4_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv3_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv2_p
add wave -noupdate -format Logic -height 15 -radix hexadecimal /tb_v4_sx_vhd/uut/lv1_p
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_v4_sx_vhd/uut/dasop
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/valid_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_pvalid
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_pvalid_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_pvalidl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_pvalidl2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_pvalidl3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_trigger2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_trigger_enable
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_trigger_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_triggerl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_triggerl2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/vsib_triggerl3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/op_fifo_inst1/wr_clk_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/op_fifo_inst1/wr_data_count
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/rst_usb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/clk_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/usb_data_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/usb_load1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/usb_load2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/fibre_bkpln_sel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/ch_sel_reg_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/vsib_fibre_num
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/fibre_no_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/no_ch_fibre1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/no_ch_fibre2_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/no_ch_fibre3_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/no_ch_fibre4_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/actual_diag
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/node
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/usbl1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_fiber/usbl
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/check_ld_low
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/usb_load_int
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/valid_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/lreset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/check_ld_low1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/usb_load_int1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_fiber/valid_load1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/do
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/drdy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/phystatus0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/phystatus1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/plllkdet
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/refclkout
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/resetdone0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/resetdone1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufstatus0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufstatus1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyteisaligned0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyteisaligned1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyterealign0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyterealign1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanbondseq0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanbondseq1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanisaligned0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanisaligned1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanrealign0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanrealign1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchariscomma0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchariscomma1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcharisk0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcharisk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondo0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondo1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxclkcorcnt0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxclkcorcnt1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadet0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadet1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdata0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdata1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdisperr0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdisperr1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidle0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidle1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxlossofsync0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxlossofsync1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxnotintable0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxnotintable1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxoversampleerr0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxoversampleerr1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxprbserr0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxprbserr1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrecclk0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrecclk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrundisp0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrundisp1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxstatus0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxstatus1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxvalid0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxvalid1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufstatus0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufstatus1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txkerr0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txkerr1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txn0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txn1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txoutclk0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txoutclk1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txp0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txp1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrundisp0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrundisp1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clkin
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/daddr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/den
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/di
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dwe
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/gtpreset
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/gtptest
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/intdatawidth
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/loopback0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/loopback1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/plllkdeten
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pllpowerdown
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbscntreset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbscntreset1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/refclkpwrdnb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufreset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufreset1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcdrreset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcdrreset1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondi0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondi1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadetuse0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadetuse1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdatawidth0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdatawidth1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdec8b10buse0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdec8b10buse1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidlereset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidlereset1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenchansync0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenchansync1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenelecidleresetb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeneqb0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeneqb1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenmcommaalign0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenmcommaalign1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenpcommaalign0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenpcommaalign1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenprbstst0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenprbstst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxensamplealign0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxensamplealign1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqmix0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqmix1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqpole0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqpole1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxn0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxn1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxp0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxp1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpmasetphase0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpmasetphase1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpolarity0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpolarity1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpowerdown0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpowerdown1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxslide0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxslide1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk20
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk21
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufdiffctrl0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufdiffctrl1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbypass8b10b0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbypass8b10b1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispmode0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispmode1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispval0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispval1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcharisk0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcharisk1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomstart0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomstart1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomtype0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomtype1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdata0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdata1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdatawidth0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdatawidth1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdetectrx0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdetectrx1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdiffctrl0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdiffctrl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txelecidle0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txelecidle1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenc8b10buse0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenc8b10buse1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenpmaphasealign
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenprbstst0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenprbstst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txinhibit0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txinhibit1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpmasetphase
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpolarity0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpolarity1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpowerdown0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpowerdown1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpreemphasis0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpreemphasis1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txreset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txreset1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk20
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk21
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_txdivsel_out_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_rxdivsel_out_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_txdivsel_out_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_rxdivsel_out_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_divsel_fb_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_divsel_ref_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_txdivsel_comm_out_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_sata_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pll_sata_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_diff_boost_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/oobdetect_threshold_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_diff_boost_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/oobdetect_threshold_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pma_cdr_scan_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pma_cdr_scan_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pma_rx_cfg_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pma_rx_cfg_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/oob_clk_divider_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_sync_filterb_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/ac_cap_dis_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/ac_cap_dis_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rcv_term_gnd_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rcv_term_gnd_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rcv_term_mid_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rcv_term_mid_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/termination_imp_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/termination_imp_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/termination_ovrd_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/termination_ctrl_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rcv_term_vttrx_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rcv_term_vttrx_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrx_invert_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrx_invert_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clkindc_b_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pcomma_detect_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/mcomma_detect_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pcomma_10b_value_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/mcomma_10b_value_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/comma_10b_enable_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/comma_double_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/align_comma_word_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dec_pcomma_detect_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dec_mcomma_detect_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dec_valid_comma_only_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pcomma_detect_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/mcomma_detect_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pcomma_10b_value_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/mcomma_10b_value_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/comma_10b_enable_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/comma_double_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/align_comma_word_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dec_pcomma_detect_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dec_mcomma_detect_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dec_valid_comma_only_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_loss_of_sync_fsm_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_los_invalid_incr_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_los_threshold_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_loss_of_sync_fsm_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_los_invalid_incr_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_los_threshold_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_buffer_use_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_decode_seq_match_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_buffer_use_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_decode_seq_match_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_min_lat_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_max_lat_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_correct_use_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_precedence_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_det_len_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_adj_len_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_keep_idle_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_insert_idle_flag_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_repeat_wait_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_use_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_1_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_2_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_3_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_4_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_1_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_2_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_3_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_4_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_enable_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_enable_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_min_lat_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_max_lat_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_correct_use_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_precedence_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_det_len_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_adj_len_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_keep_idle_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_insert_idle_flag_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_repeat_wait_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_use_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_1_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_2_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_3_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_4_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_1_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_2_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_3_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_4_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_1_enable_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk_cor_seq_2_enable_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_mode_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_level_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_len_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_use_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_1_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_2_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_3_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_4_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_1_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_2_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_3_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_4_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_enable_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_enable_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_1_max_skew_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_2_max_skew_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_mode_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_level_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_len_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_use_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_1_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_2_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_3_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_4_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_1_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_2_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_3_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_4_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_1_enable_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_seq_2_enable_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_1_max_skew_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/chan_bond_2_max_skew_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pci_express_mode_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/trans_time_from_p2_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/trans_time_non_p2_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/trans_time_to_p2_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pci_express_mode_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/trans_time_from_p2_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/trans_time_non_p2_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/trans_time_to_p2_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_status_fmt_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_buffer_use_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_xclk_sel_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_xclk_sel_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_status_fmt_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_buffer_use_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/tx_xclk_sel_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_xclk_sel_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbs_err_threshold_0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_slide_mode_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbs_err_threshold_1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rx_slide_mode_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_min_burst_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_max_burst_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_min_init_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_max_init_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_min_wake_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_max_wake_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_burst_val_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_idle_val_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/com_burst_val_0_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_min_burst_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_max_burst_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_min_init_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_max_init_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_min_wake_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_max_wake_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_burst_val_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sata_idle_val_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/com_burst_val_1_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clk25_divider_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pcs_com_cfg_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/oversample_mode_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sim_gtpreset_speedup_binary
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sim_pll_perdiv2_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sim_receiver_detect_pass0_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/sim_receiver_detect_pass1_binary
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/refclkout_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrecclk0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txoutclk0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrecclk1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txoutclk1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txp0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txn0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txp1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txn1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdata0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxnotintable0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdisperr0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcharisk0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrundisp0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchariscomma0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxvalid0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdata1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxnotintable1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdisperr1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcharisk1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrundisp1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchariscomma1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxvalid1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/resetdone0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/resetdone1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txkerr0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrundisp0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufstatus0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txkerr1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrundisp1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufstatus1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadet0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyterealign0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyteisaligned0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxlossofsync0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondo0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanbondseq0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanrealign0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanisaligned0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufstatus0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadet1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyterealign1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyteisaligned1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxlossofsync1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondo1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanbondseq1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanrealign1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanisaligned1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufstatus1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/phystatus0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/phystatus1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidle0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxstatus0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxclkcorcnt0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidle1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxstatus1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxclkcorcnt1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/plllkdet_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxprbserr0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxprbserr1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/do_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/drdy_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxoversampleerr0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxoversampleerr1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/refclkout_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrecclk0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txoutclk0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrecclk1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txoutclk1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxclkcorcnt0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxclkcorcnt1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txp0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txn0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txp1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txn1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdata0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxnotintable0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdisperr0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcharisk0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrundisp0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchariscomma0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxvalid0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdata1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxnotintable1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdisperr1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcharisk1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxrundisp1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchariscomma1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxvalid1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/resetdone0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/resetdone1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txkerr0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrundisp0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufstatus0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txkerr1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txrundisp1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufstatus1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadet0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyterealign0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyteisaligned0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxlossofsync0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondo0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanbondseq0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanrealign0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanisaligned0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufstatus0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadet1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyterealign1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbyteisaligned1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxlossofsync1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondo1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanbondseq1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanrealign1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchanisaligned1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufstatus1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/phystatus0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/phystatus1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidle0_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxstatus0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidle1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxstatus1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/plllkdet_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxprbserr0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxprbserr1_outdelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/do_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/drdy_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxoversampleerr0_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxoversampleerr1_outdelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clkin_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk20_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk20_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk21_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk21_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxp0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxn0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdata0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbypass8b10b0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcharisk0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispmode0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispval0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxp1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxn1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdata1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbypass8b10b1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcharisk1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispmode1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispval1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/gtpreset_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcdrreset0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txreset0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufreset0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcdrreset1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txreset1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufreset1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpowerdown0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpowerdown0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpowerdown1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpowerdown1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pllpowerdown_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/refclkpwrdnb_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/loopback0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/loopback1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdiffctrl0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufdiffctrl0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpreemphasis0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdiffctrl1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufdiffctrl1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpreemphasis1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeneqb0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqmix0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqpole0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeneqb1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqmix1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqpole1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/intdatawidth_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdatawidth0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdatawidth1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenpmaphasealign_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpmasetphase_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpmasetphase0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpmasetphase1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenc8b10buse0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpolarity0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txinhibit0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenc8b10buse1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpolarity1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txinhibit1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpolarity0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenpcommaalign0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenmcommaalign0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxslide0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadetuse0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdec8b10buse0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenchansync0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondi0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdatawidth0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpolarity1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenpcommaalign1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenmcommaalign1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxslide1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadetuse1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdec8b10buse1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenchansync1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondi1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdatawidth1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txelecidle0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdetectrx0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txelecidle1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdetectrx1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomstart0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomtype0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomstart1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomtype1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/plllkdeten_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenprbstst0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenprbstst0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbscntreset0_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenprbstst1_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenprbstst1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbscntreset1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dclk_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/daddr_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/di_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/den_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dwe_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxensamplealign0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxensamplealign1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidlereset0_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidlereset1_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenelecidleresetb_ipd
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/gtptest_ipd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/clkin_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk20_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk20_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txusrclk21_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxusrclk21_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxp0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxn0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdata0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbypass8b10b0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcharisk0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispmode0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispval0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxp1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxn1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdata1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbypass8b10b1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcharisk1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispmode1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txchardispval1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/gtpreset_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcdrreset0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txreset0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufreset0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcdrreset1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txreset1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxreset1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxbufreset1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpowerdown0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpowerdown0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpowerdown1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpowerdown1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/pllpowerdown_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/refclkpwrdnb_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/loopback0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/loopback1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdiffctrl0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufdiffctrl0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpreemphasis0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdiffctrl1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txbufdiffctrl1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpreemphasis1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeneqb0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqmix0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqpole0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeneqb1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqmix1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxeqpole1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/intdatawidth_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdatawidth0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdatawidth1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenpmaphasealign_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpmasetphase_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpmasetphase0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpmasetphase1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenc8b10buse0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpolarity0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txinhibit0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenc8b10buse1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txpolarity1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txinhibit1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpolarity0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenpcommaalign0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenmcommaalign0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxslide0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadetuse0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdec8b10buse0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenchansync0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondi0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdatawidth0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxpolarity1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenpcommaalign1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenmcommaalign1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxslide1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxcommadetuse1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdec8b10buse1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenchansync1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxchbondi1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxdatawidth1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txelecidle0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdetectrx0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txelecidle1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txdetectrx1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomstart0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomtype0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomstart1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txcomtype1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/plllkdeten_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenprbstst0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenprbstst0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbscntreset0_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/txenprbstst1_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenprbstst1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/prbscntreset1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dclk_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/daddr_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/di_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/den_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/dwe_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxensamplealign0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxensamplealign1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidlereset0_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxelecidlereset1_indelay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/rxenelecidleresetb_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/gtptest_indelay
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/loopback0_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/loopback1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxpowerdown0_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxpowerdown1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txpowerdown0_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txpowerdown1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchariscomma0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchariscomma1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxcharisk0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxcharisk1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxdisperr0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxdisperr1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxnotintable0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxnotintable1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchanbondseq0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchanbondseq1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchbondi0_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchbondi1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchbondo0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchbondo1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenchansync0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenchansync1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxclkcorcnt0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxclkcorcnt1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxbyteisaligned0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxbyteisaligned1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxbyterealign0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxbyterealign1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxcommadet0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxcommadet1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenmcommaalign0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenmcommaalign1_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenpcommaalign0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenpcommaalign1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxdata0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxdata1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxrecclk0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxrecclk1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxusrclk0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxusrclk1_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxusrclk20_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxusrclk21_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxcdrreset0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxcdrreset1_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxn0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxn1_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxp0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxp1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxbufstatus0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxbufstatus1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchanisaligned0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchanisaligned1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchanrealign0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxchanrealign1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxlossofsync0_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxlossofsync1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/clkin_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtpreset_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/plllkdet_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/refclkout_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/resetdone0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/resetdone1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txenpmaphasealign_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txpmasetphase_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txcharisk0_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txcharisk1_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txdata0_in
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txdata1_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txusrclk0_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txusrclk1_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txusrclk20_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txusrclk21_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txn0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txn1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txp0_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txp1_out
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txchardispmode0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txchardispmode1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txchardispval0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txchardispval1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/tied_to_ground_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/tied_to_ground_vec_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/tied_to_vcc_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/tied_to_vcc_vec_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txdata0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txusrclk20_n
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/loopback0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxelecidle0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/resetdone0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxelecidlereset0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/serialloopback0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/txusrclk21_n
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/loopback1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxelecidle1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/resetdone1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxelecidlereset1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/serialloopback1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/rocketio_wrapper_i/tile0_rocketio_wrapper_i/rxenelecidleresetb_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/led12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/an
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dn
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rd
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/gc8_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/gc8_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/extck2_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/extck2_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv1_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv1_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv2_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv2_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv3_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv3_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv4_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv4_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv5_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv5_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv6_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv6_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv7_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv7_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv8_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv8_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv9_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv9_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv10_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv10_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv11_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv11_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv12_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv12_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv65_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv65_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtck3_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtck3_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn0_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp1_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkp_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkn_112
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn0_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxn1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrxp1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxn1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgttxp1_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkp_116
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtrefclkn_116
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/gp_lines
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t0_txcharisk0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t0_txcharisk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t1_txcharisk0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t1_txcharisk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t0_rxcharisk0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t0_rxcharisk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t1_rxcharisk0
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/t1_rxcharisk1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/nu1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/nu2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/nu3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/nu4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv67_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv67_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv69_p
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lv69_n
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/deser_valid_data16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dina_sig16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/doutb_sig16
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_complete16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/deser_command
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/delay_ce
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/delay_inc_dec
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usb_command
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rden_sig16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/din
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/led_cnt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/vsib_pvalid
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/vsib_trigger
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_mode
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ch_sel_mode
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_rd_er_flag
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_1d_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_out_2d_p2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/vsib_data
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_l1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_delayed
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_rd_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds1_1a_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fdb2_1b_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds3_1c_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds6_2b_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fda7_2c_clk1buf
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck4_1d_clk2bufg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck5_2a_clk2bufg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck8_2d_clk2bufg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_1d_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2a_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2a_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2b_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2b_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2c_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2c_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2d_p1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_2d_p2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_load_delay
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_reset_chno
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fout_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_clk1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/chip_sel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/read_reg
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/read_start
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/read_started
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fifo_rdclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/burst_rd_synch
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds1_1a_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fdb2_1b_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds3_1c_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fds6_2b_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fda7_2c_clk1bufr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fck3_1c_clk2bufg
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_dina_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addra_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_wea_out16
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ram_clkb_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out5
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out6
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out7
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out8
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out9
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out10
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out11
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out12
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out13
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out14
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out15
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ram_addrb_out16
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dinl1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regcebl1_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/chsel_opreg_load
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/a1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/b1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/c1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/d1_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/a2_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/b2_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/c2_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/d2_clk
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_a1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_b1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_c1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_d1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_a2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_b2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_c2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/adfb_dat_d2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_a1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_b1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_c1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_d1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_a2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_b2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_c2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_ready_mux_d2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/ndata_ready_mux_c1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk200
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdy7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lrst1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/delay_ce_out1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/channel_selected
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/channel_no
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/usbl1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/check_ld_low
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_load_int
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_load
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ch_sel_reg
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ch_sel_reg1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ch_sel_reg_fiber
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_to_vsib
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_to_vsib
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fibre_bkpln_sel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/vsib_fibre_num
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_of_chns_to_vsib
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/ch_sel_reg_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/fiber_opreg_load
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/den_cnt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/busy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/drdy
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/eos
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/den
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/alm
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/channel
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/daddr
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/do
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_plllkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_plllkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_clkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_clkdet_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_rxclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_rxclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_rxclk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_rxclk1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/system_reset
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rxn_in_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rxp_in_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txn_out_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txp_out_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/mgtreset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wrclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk_125
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wrclk_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/wrclk1_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdclk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rdclk_sig
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxcharisk1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxcharisk0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_rxcharisk1_i
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/tile0_txdata0_i
add wave -noupdate -format Literal -radix hexadecimal /tb_v4_sx_vhd/uut/tile0_rxdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_rxcharisk0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyteisaligned0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyteisaligned1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyterealign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxbyterealign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcommadet0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxcommadet1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenmcommaalign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenmcommaalign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenpcommaalign0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_rxenpcommaalign1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone0_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/example_mgt_top_i/tile0_resetdone1_i
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile0_txdata1_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txdata0_i
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/tile1_txdata1_i
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_refclk_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_refclk_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0_txusrclk20_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1_txusrclk20_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1tx_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0rx_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile0rx_rst1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1rx_rst0
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tile1rx_rst1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispmode1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispval1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispmode2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispval2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispmode3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispval3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispmode4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/txchardispval4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/fibre_no
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/no_ch_fibre4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/actual_diag
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/tx_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f1
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f2
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f3
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_out_f4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/data_out_f4
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/node_seq_reg_f4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_f4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en3
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en4
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en5
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en6
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en7
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en8
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en9
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en10
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en11
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en12
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en13
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en14
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en15
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en16
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_enable
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_en_to_vsib
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/global_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/usb_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/refclkout_pll2_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/refclkout_pll5_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm0_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm3_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm1_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rxrecclk_dcm4_locked_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk125_mgt
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lock_out
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lock_out1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/lock_out2
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/clk125mhz
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/open_clk
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/sctn_1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/data_load_mon
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/valid_enablel1_mon
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/regceb_flag_mon
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/dasop
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/depack
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/DASOP1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_reset
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_reset
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/rstm/rx1_counter2_g
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/rstm/rx2_counter2_g
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/rstm/rx3_counter2_g
add wave -noupdate -format Literal -radix unsigned /tb_v4_sx_vhd/uut/rstm/rx4_counter2_g
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_ms2_g
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_ms2_g
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_ms2_g
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_ms2_g
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rstm/rx1_rst_internal_ctr
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rstm/rx2_rst_internal_ctr
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rstm/rx3_rst_internal_ctr
add wave -noupdate -format Literal /tb_v4_sx_vhd/uut/rstm/rx4_rst_internal_ctr
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_rst_internal
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_rst_internal
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_rst_internal
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_rst_internal
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_rst_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_rst_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_ext_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_ext_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_rst_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_rst_in
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_ext_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_ext_rst
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_rst_in1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_rst_in1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx1_int_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx2_int_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_rst_in1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_rst_in1
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx3_int_sig
add wave -noupdate -format Logic /tb_v4_sx_vhd/uut/rstm/rx4_int_sig
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {7998389 ps} 0} {{Cursor 5} {9471964 ps} 0}
WaveRestoreZoom {67258210 ps} {68157952 ps}
configure wave -namecolwidth 372
configure wave -valuecolwidth 50
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
