AGFO_FIBRE_V7_SX Project Status
Project File: agfo_fibre_V7_SX.ise Current State: Programming File Generated
Module Name: AGFO_FIBRE_V6a_SX
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
5277 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Wed Aug 12 11:26:17 2009
 
AGFO_FIBRE_V7_SX Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4,797 32,640 14%  
    Number used as Flip Flops 4,797      
Number of Slice LUTs 4,345 32,640 13%  
    Number used as logic 3,941 32,640 12%  
        Number using O6 output only 3,602      
        Number using O5 output only 178      
        Number using O5 and O6 161      
    Number used as Memory 392 12,480 3%  
        Number used as Shift Register 392      
            Number using O6 output only 392      
    Number used as exclusive route-thru 12      
Number of route-thrus 215 65,280 1%  
    Number using O6 output only 190      
    Number using O5 output only 25      
Slice Logic Distribution     
Number of occupied Slices 1,933 8,160 23%  
Number of LUT Flip Flop pairs used 6,406      
    Number with an unused Flip Flop 1,609 6,406 25%  
    Number with an unused LUT 2,061 6,406 32%  
    Number of fully used LUT-FF pairs 2,736 6,406 42%  
    Number of unique control sets 445      
IO Utilization     
Number of bonded IOBs 180 360 50%  
    IOB Flip Flops 62      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 31 132 23%  
    Number using BlockRAM only 31      
Total primitives used     
        Number of 36k BlockRAM used 21      
        Number of 18k BlockRAM used 20      
Total Memory used (KB) 1,116 4,752 23%  
Number of BUFG/BUFGCTRLs 21 32 65%  
    Number used as BUFGs 21      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 2 12 16%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 4,196,093      
Additional JTAG gate count for IOBs 9,600      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jul 29 14:59:27 200905258 Warnings110 Infos
Translation ReportCurrentWed Jul 29 14:59:53 200904 Warnings6 Infos
Map ReportCurrentWed Jul 29 15:05:18 200909 Warnings12 Infos
Place and Route ReportCurrentWed Jul 29 15:06:50 200903 Warnings2 Infos
Static Timing ReportCurrentWed Jul 29 15:07:20 2009002 Infos
Bitgen ReportCurrentWed Jul 29 15:09:10 200903 Warnings1 Info