AGFO_FIBRE_V6CP3_SX Project Status
Project File: agfo_fibre_V6cp3_SX.ise Current State: Programming File Generated
Module Name: AGFO_FIBRE_V6cp2_SX
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
5775 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Thu Jan 7 16:00:12 2010
 
AGFO_FIBRE_V6CP3_SX Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 5,269 32,640 16%  
    Number used as Flip Flops 5,269      
Number of Slice LUTs 4,984 32,640 15%  
    Number used as logic 4,551 32,640 13%  
        Number using O6 output only 4,184      
        Number using O5 output only 148      
        Number using O5 and O6 219      
    Number used as Memory 422 12,480 3%  
        Number used as Shift Register 422      
            Number using O6 output only 422      
    Number used as exclusive route-thru 11      
Number of route-thrus 194 65,280 1%  
    Number using O6 output only 159      
    Number using O5 output only 35      
Slice Logic Distribution     
Number of occupied Slices 2,063 8,160 25%  
Number of LUT Flip Flop pairs used 6,967      
    Number with an unused Flip Flop 1,698 6,967 24%  
    Number with an unused LUT 1,983 6,967 28%  
    Number of fully used LUT-FF pairs 3,286 6,967 47%  
    Number of unique control sets 491      
IO Utilization     
Number of bonded IOBs 180 360 50%  
    IOB Flip Flops 62      
    IOB Master Pads 15      
    IOB Slave Pads 15      
Specific Feature Utilization     
Number of BlockRAM/FIFO 31 132 23%  
    Number using BlockRAM only 31      
Total primitives used     
        Number of 36k BlockRAM used 21      
        Number of 18k BlockRAM used 20      
Total Memory used (KB) 1,116 4,752 23%  
Number of BUFG/BUFGCTRLs 21 32 65%  
    Number used as BUFGs 21      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 2 12 16%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 4,208,439      
Additional JTAG gate count for IOBs 9,600      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Nov 4 11:55:24 200905756 Warnings121 Infos
Translation ReportCurrentWed Nov 4 11:55:39 200904 Warnings6 Infos
Map ReportCurrentWed Nov 4 11:58:42 200909 Warnings12 Infos
Place and Route ReportCurrentWed Nov 4 11:59:32 200903 Warnings2 Infos
Static Timing ReportCurrentWed Nov 4 11:59:48 2009002 Infos
Bitgen ReportCurrentWed Nov 4 12:00:57 200903 Warnings1 Info