----------------------------------------------------------------
-- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA
-- File    : AGFO_SYNC.vhd 
-- The original source code copied from vani.
----------------------------------------------------------------
----------------------------------------------------------------
---- File    : AGFO_SYNC.vhd
---- Project : 
---- System  : orionb
----------------------------------------------------------------
-- Company: RAMAN RESEARCH INSTITUTE
-- Engineer: 
-- 
-- Create Date:    09:48:33 01/28/2008 
-- Design Name: 
-- Module Name:    
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity AGFO_SYNC is
    Port ( clk_in  			    : in  STD_LOGIC;
--			  clk_in1 			: in  STD_LOGIC;
			  sctn_in 			    : in std_logic;
			  sctn_clk_in_out     : out std_logic;			  
			  fout_clk_in_out	    : out std_logic;
			  burst_rd_synch_out  : out std_logic		  
			 ); 
           
end AGFO_SYNC;

architecture agfo of AGFO_SYNC is
--------------- Signals & Components here ----------------------
signal sctn_ctr : std_logic_vector(8 downto 0);
signal fout_ctr : std_logic_vector(6 downto 0);
signal burst_rd_ctr : std_logic_vector(10 downto 0) := "00000000000";
signal sctn_in_7clk,sctn_out,sctn_out_low ,
       fout_clk_in_local, burst_rd_synch_local  : std_logic;
signal sctn_in_cnt : std_logic_vector(2 downto 0);
--constant SCTN_DELAY : integer := 310 ; -- SCTN DELAY CONTROL WITH FOUT 
--constant SCTN_DELAY : integer := 80 ; -- This delay is used to adjust the FOUT in sync with adfb data 19may09
--constant SCTN_DELAY : integer := 90 ; -- This delay is used to adjust the FOUT in sync with adfb data 19may09
--constant CLK_RATIO : integer := 7 ;   -- 165mhz to DAS clk ratio
constant FOUT_PERIOD : integer := 127 ; -- FOUT period is 128 clk_in cycles
constant BURST_RD_SYNCH_PERIOD : integer := 1199 ; -- FOUT period; 1024+ FOUT period for AgFo reading

constant SCTN_DELAY : integer := 107 ; -- This delay is used to adjust the FOUT in sync with adfb data 19may09                                                   -- and some 80+ FOUT period from ADFB

begin
----------------------------------------------------------------
------------------ 16 bit shift register -----------------------
process(clk_in)
begin
 if(clk_in'event and clk_in = '1') then
    if sctn_in <= '0' then
		sctn_ctr <= (others => '0');
		sctn_out <= '1';
		sctn_out_low <= '1';
	 elsif (sctn_out_low = '1') then
		sctn_ctr <= sctn_ctr + '1';
		if sctn_ctr  = 	SCTN_DELAY then
			sctn_out <= '0';
			sctn_out_low <= '0';
			sctn_ctr<= (others => '0');
		end if;	
	 end if;	
	 if sctn_out = '0' then
		sctn_out <= '1';
	 end if;	
 end if;
end process; 

process(clk_in,sctn_out)
begin
 if(clk_in'event and clk_in = '1') then
   if(sctn_out = '0') then
		fout_ctr <= (others => '0');
		fout_clk_in_out <= '1';
		fout_clk_in_local <= '1';
		if(burst_rd_ctr = BURST_RD_SYNCH_PERIOD) then
		  burst_rd_ctr <= (others => '0');
		  burst_rd_synch_out <= '1';
		  burst_rd_synch_local <= '1';
		else
        burst_rd_ctr <= burst_rd_ctr + 1;
      end if;		  
	else
		fout_ctr <= fout_ctr + '1';
		if fout_ctr = FOUT_PERIOD then
			fout_clk_in_out <= '1';
			fout_clk_in_local <= '1';
			fout_ctr <= (others => '0');
			if(burst_rd_ctr = BURST_RD_SYNCH_PERIOD) then
		       burst_rd_ctr <= (others => '0');
		       burst_rd_synch_out <= '1';
				 burst_rd_synch_local <= '1';
		   else
             burst_rd_ctr <= burst_rd_ctr + 1;
         end if;		  		
		end if;
		

	end if;	
	
	if fout_clk_in_local = '1' then
		fout_clk_in_out <= '0';
		fout_clk_in_local <= '0';
	end if;	

	if burst_rd_synch_local = '1' then
	   burst_rd_synch_local <= '0';
		burst_rd_synch_out <= '0';
	end if;		
	
	sctn_clk_in_out <= sctn_out;	
 end if; 
end process;

--sctn:process(clk_in,sctn_in)	     
--begin
--   if clk_in'event and clk_in = '1' then
--	  if sctn_out  = '0' then
--		  sctn_in_7clk <= '0';
--		  sctn_in_cnt <= (others => '0');
--	  end if;	  
--	  if sctn_in_7clk = '0' then 
--		  sctn_in_cnt <=	  sctn_in_cnt + '1';
--	     if sctn_in_cnt < CLK_RATIO then
--			 sctn_in_7clk <= '0';
--		  else
--		 	 sctn_in_7clk <= '1';
--			 sctn_in_cnt <= (others => '0');
--		  end if;	 
--  		end if;		
--	end if;
--end process sctn;	

--process(clk_in1)
--begin
-- if clk_in1'event and clk_in1 = '1' then
--    sctn_clk_in1_out <= sctn_in_7clk;
-- end if;
--end process; 

end agfo;
----------- end of file : AGFO_SYNC.vhd ----------------------