-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:10:24 03/09/2009 -- Design Name: PACK_MGT_TOP_V1 -- Module Name: D:/MWA_AGFOFIBRE_SIM_FEB08/PACK_MGT_v1/pack_mgt_v1/PACK_MGT_TB.vhd -- Project Name: pack_mgt_v1 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: PACK_MGT_TOP_V1 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY PACK_MGT_TB_vhd IS END PACK_MGT_TB_vhd; ARCHITECTURE behavior OF PACK_MGT_TB_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT PACK_MGT_TOP_V1 PORT( -- mgtreset: IN std_logic; mgtck3_n : IN std_logic; mgtck3_p : IN std_logic; lv67_p : IN std_logic; lv67_n : IN std_logic; lv69_p : IN std_logic; lv69_n : IN std_logic; An : IN std_logic_vector(7 downto 0); WR : IN std_logic; RD : IN std_logic; MGTRXP0_112 : IN std_logic; MGTRXN0_112 : IN std_logic; MGTRXN1_112 : IN std_logic; MGTRXP1_112 : IN std_logic; MGTREFCLKP_112 : IN std_logic; MGTREFCLKN_112 : IN std_logic; MGTRXP0_116 : IN std_logic; MGTRXN0_116 : IN std_logic; MGTRXN1_116 : IN std_logic; MGTRXP1_116 : IN std_logic; MGTREFCLKP_116 : IN std_logic; MGTREFCLKN_116 : IN std_logic; Dn : INOUT std_logic_vector(7 downto 0); MGTTXP0_112 : OUT std_logic; MGTTXN0_112 : OUT std_logic; MGTTXN1_112 : OUT std_logic; MGTTXP1_112 : OUT std_logic; MGTTXP0_116 : OUT std_logic; MGTTXN0_116 : OUT std_logic; MGTTXN1_116 : OUT std_logic; MGTTXP1_116 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL mgtck3_n : std_logic := '0'; SIGNAL mgtck3_p : std_logic := '0'; SIGNAL lv67_p : std_logic := '0'; SIGNAL lv67_n : std_logic := '0'; SIGNAL lv69_p : std_logic := '0'; SIGNAL lv69_n : std_logic := '0'; SIGNAL WR : std_logic := '0'; SIGNAL RD : std_logic := '0'; SIGNAL MGTRXP0_112 : std_logic := '0'; SIGNAL MGTRXN0_112 : std_logic := '0'; SIGNAL MGTRXN1_112 : std_logic := '0'; SIGNAL MGTRXP1_112 : std_logic := '0'; SIGNAL MGTREFCLKP_112 : std_logic := '0'; SIGNAL MGTREFCLKN_112 : std_logic := '0'; SIGNAL MGTRXP0_116 : std_logic := '0'; SIGNAL MGTRXN0_116 : std_logic := '0'; SIGNAL MGTRXN1_116 : std_logic := '0'; SIGNAL MGTRXP1_116 : std_logic := '0'; SIGNAL MGTREFCLKP_116 : std_logic := '0'; SIGNAL MGTREFCLKN_116 : std_logic := '0'; SIGNAL An : std_logic_vector(7 downto 0) := (others=>'0'); --BiDirs SIGNAL Dn : std_logic_vector(7 downto 0); --Outputs SIGNAL MGTTXP0_112 : std_logic; SIGNAL MGTTXN0_112 : std_logic; SIGNAL MGTTXN1_112 : std_logic; SIGNAL MGTTXP1_112 : std_logic; SIGNAL MGTTXP0_116 : std_logic; SIGNAL MGTTXN0_116 : std_logic; SIGNAL MGTTXN1_116 : std_logic; SIGNAL MGTTXP1_116 : std_logic; SIGNAL clk165,clk_330MHz : std_logic; SIGNAL sctn_in ,rstin,RESET,mgt_reset: std_logic := '0'; component SIM_RESET_MGT_MODEL port ( GSR_IN : in std_logic ); end component; SIGNAL c1 : std_logic_vector(9 downto 0):=(others => '0'); SIGNAL sctn_counter1 : std_logic_vector(23 downto 0):=(others => '0'); --FOR USB MODULE SIGNAL USB_CLK : STD_LOGIC; --:='0'; SIGNAL t1_uaddr : std_logic_vector(1 downto 0); SIGNAL t2_uaddr : std_logic; SIGNAL t3_uaddr : std_logic_vector(4 downto 0):=(OTHERS => '0'); SIGNAL counter : std_logic_vector(15 downto 0):=(OTHERS => '0'); SIGNAL st : std_logic_vector(4 downto 0):=(OTHERS => '0'); SIGNAL COMMAND : std_logic_vector(4 downto 0); SIGNAL DATA: std_logic_vector(7 downto 0); SIGNAL inc_st,resetst,RST_CTR,INC_STATE1,LOAD_DATA,INC_CH_CTR,chsel_done,START_WRITING: std_logic := '0'; SIGNAL START_COUNTER,START_COUNTER1,START_DONE,INC_GAIN_CTR,POL1_DONE,POL2_DONE: std_logic := '0'; SIGNAL INT_STATE_CTR ,INT_STATE_CTR1: STD_LOGIC_VECTOR( 3 DOWNTO 0):=(OTHERS => '0'); SIGNAL STATE_CTR1 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (OTHERS => '0'); SIGNAL CH_CTR : STD_LOGIC_VECTOR(5 DOWNTO 0):=(OTHERS => '0'); SIGNAL CH_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):=(OTHERS => '0'); SIGNAL DONE1,DONE2,DONE3,DONE3a,DONE3b,USB_OP_COMPLETE,USB_OP_COMPLETE1: STD_LOGIC:='0'; SIGNAL P1_DONE,P2_DONE,INC_RAMP_CTR,LOAD_RDATA : STD_LOGIC:='0'; SIGNAL ctra,dummyctra : std_logic_vector(31 downto 0) := X"00000000"; BEGIN RESET <= '0' , '1' AFTER 200 NS; mgt_reset <= '1', '0' after 200 ns; sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL port map ( GSR_IN => mgt_reset ); -- Instantiate the Unit Under Test (UUT) uut: PACK_MGT_TOP_V1 PORT MAP( -- mgtreset => mgt_reset, mgtck3_n => mgtck3_n, mgtck3_p => mgtck3_p, lv67_p => lv67_p, lv67_n => lv67_n, lv69_p => lv69_p, lv69_n => lv69_n, An => An, Dn => Dn, WR => WR, RD => RD, MGTTXP0_112 => MGTTXP0_112, MGTTXN0_112 => MGTTXN0_112, MGTRXP0_112 => MGTRXP0_112, MGTRXN0_112 => MGTRXN0_112, MGTRXN1_112 => MGTRXN1_112, MGTRXP1_112 => MGTRXP1_112, MGTTXN1_112 => MGTTXN1_112, MGTTXP1_112 => MGTTXP1_112, MGTREFCLKP_112 => MGTREFCLKP_112, MGTREFCLKN_112 => MGTREFCLKN_112, MGTTXP0_116 => MGTTXP0_116, MGTTXN0_116 => MGTTXN0_116, MGTRXP0_116 => MGTRXP0_116, MGTRXN0_116 => MGTRXN0_116, MGTRXN1_116 => MGTRXN1_116, MGTRXP1_116 => MGTRXP1_116, MGTTXN1_116 => MGTTXN1_116, MGTTXP1_116 => MGTTXP1_116, MGTREFCLKP_116 => MGTREFCLKP_116, MGTREFCLKN_116 => MGTREFCLKN_116 ); mgtck3_p <= clk165; mgtck3_n <= not clk165; lv67_p <= clk165; lv67_n <= not lv67_p; lv69_p <= sctn_in; lv69_p <= not lv69_p; MGTREFCLKP_112 <= clk165; MGTREFCLKN_112 <= not clk165; MGTREFCLKP_112 <= clk165; MGTREFCLKN_112 <= not clk165; MGTRXP0_112 <= MGTTXP0_112; MGTRXN0_112 <= MGTTXN0_112; MGTRXN1_112 <= MGTTXN1_112; MGTRXP1_112 <= MGTTXP1_112; MGTREFCLKP_116 <= clk165; MGTREFCLKN_116 <= not clk165; MGTRXP0_116 <= MGTTXP0_116; MGTRXN0_116 <= MGTTXN0_116; MGTRXN1_116 <= MGTTXN1_116; MGTRXP1_116 <= MGTTXP1_116; clk_330: process -- Generate clock waveform of 330 MHz begin clk_330MHz<= '1', '0' after 1.5 ns, '1' after 3 ns, '0' after 4.5 ns; wait for 6 ns ; end process clk_330; clk_165: process -- Generate clock waveform of 330 MHz begin clk165<= '1', '0' after 4 ns, '1' after 8 ns, '0' after 12 ns; wait for 16 ns ; end process clk_165; SCTN_p: process(clk165) -- generate clock waveform begin if clk165'event and clk165 = '1' then sctn_counter1 <= sctn_counter1 + '1'; sctn_in <= '1'; if sctn_counter1 = 32767 then --8388608 then sctn_in <= '0'; sctn_counter1 <= (others => '0'); end if; end if; end process SCTN_p; --============================================================================================== t1_uaddr<= "00"; t3_uaddr<= COMMAND; --"0001";--"0001";--"0000"; An <= t3_uaddr & t2_uaddr & t1_uaddr; Dn <= DATA; USB_CLKp: process -- generate clock waveform begin USB_CLK <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns; wait for 400 ns ; end process USB_CLKp; process(RESET,USB_CLK) begin if USB_CLK'event and USB_CLK = '1' then if RESET = '0' then st <= (others => '0'); elsif inc_st = '1' then st <= st + '1'; end if; end if; end process; PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF RESET = '0' THEN COMMAND <= (OTHERS=>'0'); WR <= '0'; START_COUNTER <= '0'; INC_GAIN_CTR <= '0'; POL1_DONE <= '0'; POL2_DONE <= '0'; t2_uaddr<= '0'; resetst <= '0'; inc_st<= '0'; RST_CTR<= '0'; START_COUNTER1 <= '0'; LOAD_DATA <= '0'; chsel_done <= '0'; DONE1 <= '0'; DONE2 <= '0'; DONE3 <= '0'; DONE3a <= '0'; DONE3b <= '0'; USB_OP_COMPLETE <= '0'; P1_DONE <= '0'; P2_DONE <= '0'; INC_RAMP_CTR <= '0'; LOAD_RDATA <= '0'; ELSE CASE st IS WHEN "00000" => COMMAND <= "00000"; WR <= '0'; inc_st <= '1'; WHEN "00001" => WR <= '1'; inc_st <= '1'; WHEN "00010" => WR <= '1'; inc_st <= '1'; WHEN "00011" => WR <= '1'; inc_st <= '1'; WHEN "00100" => WR <= '1'; inc_st <= '1'; WHEN "00101" => WR <= '0'; inc_st <= '0'; START_COUNTER <= '1'; WHEN "00110" => IF INT_STATE_CTR = 0 THEN COMMAND <= "00001"; DATA <= (OTHERS => '0'); WR <= '1'; inc_st <= '0'; ELSIF INT_STATE_CTR = 1 THEN COMMAND <= "00001"; DATA <= (OTHERS => '0'); WR <= '0'; -- USB_OP_COMPLETE <= '1'; ELSIF INT_STATE_CTR = 2 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR = 3 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR = 4 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR = 5 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR = 6 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR = 7 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR = 8 THEN DATA <= X"00"; WR <= '1'; START_COUNTER <= '0'; ELSIF INT_STATE_CTR = 9 THEN DATA <= X"00"; WR <= '0'; START_COUNTER <= '0'; inc_st <= '1'; t2_uaddr<= '0'; END IF; -- WHEN "00111" => -- IF t2_uaddr = '0' AND POL1_DONE = '0' then -- READ_DATA <= READ_DATA1; -- ELSIF t2_uaddr = '1' AND POL1_DONE = '1' then -- READ_DATA <= READ_DATA2; -- END IF; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00010"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= READ_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00010"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_GAIN_CTR <= '1'; -- DATA <= READ_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND POL2_DONE = '0' THEN -- START_COUNTER1<= '1'; -- -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= READ_DATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_GAIN_CTR <= '0'; ---- START_COUNTER1<= '1'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= READ_DATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= READ_DATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=READ_DATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= READ_DATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= READ_DATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= READ_DATA(31 downto 24); -- WR <= '1'; -- INC_GAIN_CTR <= '1'; -- IF GAIN_CTR = 256 THEN -- RST_CTR <= '1'; -- END IF; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= READ_DATA(31 downto 24); -- WR <= '0'; -- INC_GAIN_CTR <= '0'; -- START_COUNTER1 <= '0'; -- IF GAIN_CTR = 128 THEN -- t2_uaddr<= '1'; -- END IF; -- IF GAIN_CTR = 128 THEN -- POL1_DONE <= '1'; -- END IF; -- -- IF GAIN_CTR = 127 THEN -- LOAD_DATA <= '1'; -- END IF; -- -- -- IF GAIN_CTR = 256 THEN -- INC_GAIN_CTR <= '0'; -- START_COUNTER1<= '0'; -- POL2_DONE <= '1'; -- inc_st <= '1'; -- t2_uaddr<= '0'; -- RST_CTR <= '0'; -- ---- ELSE ---- inc_st <= '0'; -- END IF; -- END IF; -- END IF; -- -- WHEN "01000" => -- inc_st <= '0'; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00011"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= CH_DATA(7 downto 0); -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00011"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_CH_CTR <= '1'; -- DATA <= CH_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND chsel_done = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= CH_DATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_CH_CTR <= '0'; ---- START_COUNTER1<= '1'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= CH_DATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= CH_DATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=CH_DATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= CH_DATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= CH_DATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= CH_DATA(31 downto 24); -- WR <= '1'; -- INC_CH_CTR <= '1'; -- IF CH_CTR = 33 THEN -- RST_CTR <= '1'; -- -- END IF; -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= CH_DATA(31 downto 24); -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- -- IF CH_CTR = 33 THEN -- t2_uaddr<= '1'; -- INC_CH_CTR <= '0'; -- START_COUNTER1<= '0'; -- inc_st <= '1'; -- chsel_done <= '1'; -- RST_CTR <= '0'; -- -- END IF; -- END IF; -- END IF; -- WHEN "01001" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00100"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"02"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00100"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"02"; -- -- ELSIF STATE_CTR1 = 2 AND DONE1 = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"02"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"02"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"02"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"02"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- START_COUNTER1 <= '0'; -- DONE1 <= '1'; -- RST_CTR <= '0'; -- inc_st <= '1'; -- -- -- END IF; -- END IF; WHEN "00111" => IF STATE_CTR1 = 0 THEN -- 24 channels enabled WR <= '1'; COMMAND <= "00101"; inc_st <= '0'; INC_STATE1 <= '1'; DATA <= X"FB"; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00101"; WR <= '0'; INC_STATE1 <= '0'; DATA <= X"FB"; ELSIF STATE_CTR1 = 2 AND DONE2 = '0' THEN START_COUNTER1<= '1'; IF INT_STATE_CTR1 = 0 THEN DATA <= X"FB"; WR <= '1'; INC_STATE1 <= '0'; ELSIF INT_STATE_CTR1 = 1 THEN DATA <= X"FB"; WR <= '0'; ELSIF INT_STATE_CTR1 = 2 THEN DATA <= X"0F"; WR <= '1'; ELSIF INT_STATE_CTR1 = 3 THEN DATA <= X"0F"; WR <= '0'; ELSIF INT_STATE_CTR1 = 4 THEN DATA <= X"3F"; WR <= '1'; ELSIF INT_STATE_CTR1 = 5 THEN DATA <= X"3F"; WR <= '0'; ELSIF INT_STATE_CTR1 = 6 THEN DATA <= X"00"; WR <= '1'; RST_CTR <= '1'; ELSIF INT_STATE_CTR1 = 7 THEN DATA <= X"00"; WR <= '0'; INC_CH_CTR <= '0'; START_COUNTER1 <= '0'; RST_CTR <= '0'; DONE2 <= '1'; inc_st <= '1'; END IF; END IF; WHEN "01000" => IF STATE_CTR1 = 0 THEN WR <= '1'; COMMAND <= "00110"; inc_st <= '0'; INC_STATE1 <= '1'; DATA <= X"01"; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00110"; WR <= '0'; INC_STATE1 <= '0'; DATA <= X"01"; ELSIF STATE_CTR1 = 2 AND DONE3 = '0' THEN START_COUNTER1<= '1'; IF INT_STATE_CTR1 = 0 THEN DATA <= X"01"; WR <= '1'; INC_STATE1 <= '0'; ELSIF INT_STATE_CTR1 = 1 THEN DATA <= X"01"; WR <= '0'; ELSIF INT_STATE_CTR1 = 2 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR1 = 3 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR1 = 4 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR1 = 5 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR1 = 6 THEN DATA <= X"00"; WR <= '1'; RST_CTR <= '1'; ELSIF INT_STATE_CTR1 = 7 THEN DATA <= X"00"; WR <= '0'; INC_CH_CTR <= '0'; START_COUNTER1 <= '0'; RST_CTR <= '0'; DONE3 <= '1'; inc_st <= '1'; USB_OP_COMPLETE <= '1'; END IF; END IF; ------------------------------------------------------------------------------------ -- WHEN "01100" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00110"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"00"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00110"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"00"; -- -- ELSIF STATE_CTR1 = 2 AND DONE3a = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"00"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- RST_CTR <= '0'; -- DONE3a <= '1'; -- inc_st <= '1'; -- -- -- END IF; -- END IF; -- -------------------------------------------------------------------------------------- -- WHEN "01101" => ---- IF t2_uaddr = '0' AND POL1_DONE = '0' then ---- READ_DATA <= READ_DATA1; ---- ELSIF t2_uaddr = '1' AND POL1_DONE = '1' then ---- READ_DATA <= READ_DATA2; ---- END IF; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00111"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= RAMPDATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00111"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_RAMP_CTR <= '1'; -- DATA <= RAMPDATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND P2_DONE = '0' THEN -- START_COUNTER1<= '1'; -- -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= RAMPDATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_RAMP_CTR <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= RAMPDATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= RAMPDATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=RAMPDATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= RAMPDATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= RAMPDATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= RAMPDATA(31 downto 24); -- WR <= '1'; -- INC_RAMP_CTR <= '1'; -- IF IPRAMP_CTR = 64 THEN -- RST_CTR <= '1'; -- END IF; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= RAMPDATA(31 downto 24); -- WR <= '0'; -- INC_RAMP_CTR <= '0'; -- START_COUNTER1 <= '0'; -- -- -- IF IPRAMP_CTR = 64 THEN -- INC_RAMP_CTR <= '0'; -- START_COUNTER1<= '0'; -- P2_DONE <= '1'; -- inc_st <= '1'; -- RST_CTR <= '0'; -- USB_OP_COMPLETE <= '1'; -- -- END IF; -- END IF; -- END IF; ------------------------------------------------------------------------------------ WHEN "10001" => IF STATE_CTR1 = 0 THEN WR <= '1'; COMMAND <= "00000"; inc_st <= '0'; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00000"; WR <= '0'; INC_STATE1 <= '0'; END IF; WHEN OTHERS => WR <= '0'; RD <= '0'; END CASE; END IF; END IF; END PROCESS; PROCESS(USB_CLK) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF START_COUNTER = '1' THEN INT_STATE_CTR <= INT_STATE_CTR + '1'; ELSE INT_STATE_CTR <= INT_STATE_CTR; END IF; IF INT_STATE_CTR = 9 THEN INT_STATE_CTR <= (OTHERS => '0'); END IF; END IF; END PROCESS; -------------------------------------------------------------------------- PROCESS(USB_CLK) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF INC_STATE1 = '1' THEN STATE_CTR1 <= STATE_CTR1 + '1'; ELSE STATE_CTR1 <= STATE_CTR1; END IF; IF RST_CTR = '1' THEN STATE_CTR1 <= (OTHERS => '0'); END IF; END IF; END PROCESS; PROCESS(USB_CLK) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF START_COUNTER1= '1' THEN INT_STATE_CTR1 <= INT_STATE_CTR1 + '1'; ELSE INT_STATE_CTR1 <= INT_STATE_CTR1; END IF; IF INT_STATE_CTR1 = 7 THEN INT_STATE_CTR1 <= (OTHERS => '0'); END IF; END IF; END PROCESS; --------------------------------------------------------- -- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_GAIN_CTR = '1' THEN -- GAIN_CTR <= GAIN_CTR + '1'; -- ELSE -- GAIN_CTR <= GAIN_CTR; -- END IF; -- -- IF GAIN_CTR = 257 THEN -- GAIN_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; ----------------------------------------------------------- -- -- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_CH_CTR = '1' THEN -- CH_CTR <= CH_CTR + '1'; -- ELSE -- CH_CTR <= CH_CTR; -- END IF; -- -- IF CH_CTR = 34 THEN --and P2_DONE = '1' THEN -- CH_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; -- --------------------------------------------------------- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_RAMP_CTR = '1' THEN -- IPRAMP_CTR <= IPRAMP_CTR + '1'; -- ELSE -- IPRAMP_CTR <= IPRAMP_CTR; -- END IF; -- -- IF IPRAMP_CTR = 65 then --AND P2_DONE = '1' THEN -- IPRAMP_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; END;