---------------------------------------------------------------------------------- -- Company: RRI -- Engineer: Srivani K.S -- -- Create Date: 17:44:01 05/09/2008 -- Design Name: -- Module Name: sysmon_01_lx - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity PACK_MGT_TOP_V1 is Port ( --mgtreset : in STD_LOGIC; mgtck3_n : in STD_LOGIC; mgtck3_p : in STD_LOGIC; lv67_p : in STD_LOGIC; -- GCLK IN lv67_n : in STD_LOGIC; lv69_p : in STD_LOGIC; -- SCTN IN lv69_n : in STD_LOGIC; -- valid_regceb: in STD_LOGIC; -- valid_data : in STD_LOGIC_VECTOR; An : in std_logic_vector(7 downto 0); Dn : inout std_logic_vector(7 downto 0); WR : in std_logic; RD : in std_logic; --- MGT_112 interface MGTTXP0_112 : out std_logic; MGTTXN0_112 : out std_logic; MGTRXP0_112 : in std_logic; MGTRXN0_112 : in std_logic; MGTRXN1_112 : in std_logic; MGTRXP1_112 : in std_logic; MGTTXN1_112 : out std_logic; MGTTXP1_112 : out std_logic; MGTREFCLKP_112 : in std_logic; MGTREFCLKN_112 : in std_logic; -- --- MGT_114 interface -- MGTTXP0_114 : out std_logic; -- MGTTXN0_114 : out std_logic; -- MGTRXP0_114 : in std_logic; -- MGTRXN0_114 : in std_logic; -- -- MGTRXN1_114 : in std_logic; -- MGTRXP1_114 : in std_logic; -- MGTTXN1_114 : out std_logic; -- MGTTXP1_114 : out std_logic; -- -- MGTREFCLKP_114 : in std_logic; -- MGTREFCLKN_114 : in std_logic; --- MGT_116 interface MGTTXP0_116 : out std_logic; MGTTXN0_116 : out std_logic; MGTRXP0_116 : in std_logic; MGTRXN0_116 : in std_logic; MGTRXN1_116 : in std_logic; MGTRXP1_116 : in std_logic; MGTTXN1_116 : out std_logic; MGTTXP1_116 : out std_logic; MGTREFCLKP_116 : in std_logic; MGTREFCLKN_116 : in std_logic; ------------monitoring points t0_txcharisk0 : out std_logic; t0_txcharisk1 : out std_logic; t1_txcharisk0 : out std_logic; t1_txcharisk1 : out std_logic; t2_txcharisk0 : out std_logic; t2_txcharisk1 : out std_logic; t3_txcharisk0 : out std_logic; t3_txcharisk1 : out std_logic; t0_rxcharisk0 : out std_logic; t0_rxcharisk1 : out std_logic; t1_rxcharisk0 : out std_logic; t1_rxcharisk1 : out std_logic; t2_rxcharisk0 : out std_logic; t2_rxcharisk1 : out std_logic; t3_rxcharisk0 : out std_logic; t3_rxcharisk1 : out std_logic; mgtrst_out : out std_logic ); end PACK_MGT_TOP_V1; architecture Behavioral of PACK_MGT_TOP_V1 is -- sysmon interface signals signal den_cnt : std_logic_vector(15 downto 0); signal BUSY,DRDY,EOS,DEN : std_logic; signal ALM : std_logic_vector(2 downto 0); signal CHANNEL : std_logic_vector(4 downto 0); signal DADDR : std_logic_vector(6 downto 0); signal DO : std_logic_vector(15 downto 0); -- mgt_signal interface signal tile0_plllkdet_i,tile1_plllkdet_i,tile0_clkdet_i,tile1_clkdet_i : std_logic; signal tile0_rxclk0_i,tile0_rxclk1_i,tile1_rxclk0_i : std_logic; signal system_reset : std_logic; signal rxn_in_i,rxp_in_i,txn_out_i,txp_out_i : std_logic_vector(3 downto 0); signal tile0_rxdata0_i : std_logic_vector(15 downto 0); signal tile0_rxdata1_i : std_logic_vector(15 downto 0); signal tile1_rxdata0_i : std_logic_vector(15 downto 0); signal tile1_rxdata1_i : std_logic_vector(15 downto 0); component EXAMPLE_MGT_TOP generic ( EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 0; EXAMPLE_LANE_WITH_START_CHAR : integer := 0; EXAMPLE_WORDS_IN_BRAM : integer := 512; EXAMPLE_SIM_GTPRESET_SPEEDUP : integer := 1; EXAMPLE_SIM_PLL_PERDIV2 : bit_vector:= x"190"; EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets ); port ( TILE0_REFCLK_PAD_N_IN : in std_logic; TILE0_REFCLK_PAD_P_IN : in std_logic; TILE1_REFCLK_PAD_N_IN : in std_logic; TILE1_REFCLK_PAD_P_IN : in std_logic; GTPRESET_IN : in std_logic; TILE0_PLLLKDET_OUT : out std_logic; TILE1_PLLLKDET_OUT : out std_logic; TILE0_CLKDET_OUT : out std_logic; TILE1_CLKDET_OUT : out std_logic; GTP_SYSTEM_RESET : out std_logic; TILE0_RXCLK0_OUT : out std_logic; TILE0_RXCLK1_OUT : out std_logic; TILE1_RXCLK0_OUT : out std_logic; TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA1_OUT : out std_logic_vector(15 downto 0); RXN_IN : in std_logic_vector(3 downto 0); RXP_IN : in std_logic_vector(3 downto 0); TXN_OUT : out std_logic_vector(3 downto 0); TXP_OUT : out std_logic_vector(3 downto 0); tile0_txcharisk0_i : in std_logic_vector(1 downto 0); tile0_txcharisk1_i : in std_logic_vector(1 downto 0); tile1_txcharisk0_i : in std_logic_vector(1 downto 0); tile1_txcharisk1_i : in std_logic_vector(1 downto 0); tile0_txdata0_i : in std_logic_vector(15 downto 0); tile0_txdata1_i : in std_logic_vector(15 downto 0); tile1_txdata0_i : in std_logic_vector(15 downto 0); tile1_txdata1_i : in std_logic_vector(15 downto 0); CLK_125 : out std_logic; tile0_rxcharisk0_i : out std_logic_vector(1 downto 0); tile0_rxcharisk1_i : out std_logic_vector(1 downto 0); tile1_rxcharisk0_i : out std_logic_vector(1 downto 0); tile1_rxcharisk1_i : out std_logic_vector(1 downto 0) ); end component; COMPONENT trans_test2 Port ( clk_165 : in STD_LOGIC; clk_125 : in STD_LOGIC; rst : in STD_LOGIC; sctn_in : in STD_LOGIC; valid_regceb : in STD_LOGIC; valid_data : in STD_LOGIC_VECTOR (159 downto 0); usb_command : in STD_LOGIC_VECTOR(31 downto 0); usb_load : in STD_LOGIC; ---Outputs dout1 : out STD_LOGIC_VECTOR (15 downto 0); dout2 : out STD_LOGIC_VECTOR (15 downto 0); dout3 : out STD_LOGIC_VECTOR (15 downto 0); dout4 : out STD_LOGIC_VECTOR (15 downto 0); charisk1 : out STD_LOGIC_VECTOR (1 downto 0); charisk2 : out STD_LOGIC_VECTOR (1 downto 0); charisk3 : out STD_LOGIC_VECTOR (1 downto 0); charisk4 : out STD_LOGIC_VECTOR (1 downto 0); -- actual_diag : out STD_LOGIC; ip_dpram_en : out STD_LOGIC ); end COMPONENT; COMPONENT usb_agfo1 Port ( CLK : in std_logic; RESET_IN : IN STD_LOGIC; U_WR_usb : IN STD_LOGIC; U_RD_usb : IN STD_LOGIC; U_ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CHIP_SEL : IN STD_LOGIC_VECTOR(1 downto 0); U_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); READ_REG : IN STD_LOGIC_VECTOR(31 DOWNTO 0); POL_SELECTION : OUT STD_LOGIC; PIPELINE_EN : OUT STD_LOGIC; OUTPUT_REG : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); WALSH_WREN_out : OUT STD_LOGIC; WALSH_OPREG_LOAD : OUT STD_LOGIC; GAIN_WREN1_out : OUT STD_LOGIC; GAIN_WREN2_out : OUT STD_LOGIC; CHSEL_WREN_out : OUT STD_LOGIC; OPREG_LOAD_out : OUT STD_LOGIC; SER_WREN_out : OUT STD_LOGIC; SER_OPREG_LOAD : OUT STD_LOGIC; SCTN_WREN_out : OUT STD_LOGIC; SCTN_OPREG_LOAD : OUT STD_LOGIC; EXTRST_WR_EN : OUT STD_LOGIC; RST_OPREG_LOAD : OUT STD_LOGIC; OPREG_RDEN : OUT STD_LOGIC ); END COMPONENT; component fifo_clk_gen1 Port ( clk_in : in std_logic; reset_in : in std_logic; clk_out : out std_logic; clk200 : out std_logic; lock_out : out std_logic ); end component; component rst_module1_usb Port ( clk_in : in STD_LOGIC; -- ext_rst_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load : in std_logic; -- counter_out : out std_logic_vector(15 downto 0); ms6a_out : out std_logic; reset_out : out std_logic; MGT_RESET : out std_logic ); end component; signal chip_sel : std_logic_vector(1 downto 0) := "00"; signal CLK_125 ,USB_CLK,WRCLK_sig,WRCLK1_sig,RDCLK,RDCLK_sig: std_logic; signal FIBRE_LOAD,gtp_reset,WRCLK ,clk200: std_logic; signal usb_command : std_logic_vector(31 downto 0) := X"00000000"; signal read_reg : std_logic_vector(31 downto 0); signal tile0_rxcharisk0_i : std_logic_vector(1 downto 0); signal tile0_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile1_rxcharisk0_i : std_logic_vector(1 downto 0); signal tile1_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile0_txcharisk0_i : std_logic_vector(1 downto 0); signal tile0_txcharisk1_i : std_logic_vector(1 downto 0); signal tile1_txcharisk0_i : std_logic_vector(1 downto 0); signal tile1_txcharisk1_i : std_logic_vector(1 downto 0); signal tile0_txdata0_i : std_logic_vector(15 downto 0); signal tile0_txdata1_i : std_logic_vector(15 downto 0); signal tile1_txdata0_i : std_logic_vector(15 downto 0); signal tile1_txdata1_i : std_logic_vector(15 downto 0); signal clk_165 : std_logic; signal valid_data : std_logic_vector(159 downto 0); signal valid_regceb : std_logic; signal RST_LOAD : std_logic; signal mgtreset,rstin,SCTN,SCTN_L1 : std_logic; component SIM_RESET_MGT_MODEL port ( GSR_IN : in std_logic ); end component; ---------------------------------------------------------------------------------------- begin sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL port map ( GSR_IN => mgtreset ); rstm : rst_module1_usb port map( clk_in => clk_165, usb_data_in => usb_command, usb_load => RST_LOAD, ms6a_out => open, reset_out => rstin, MGT_RESET => mgtreset ); clk165 : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => true, IBUF_DELAY_VALUE => "0", IOSTANDARD => "LVDS_25") port map ( O => clk_165, -- Clock buffer output I => lv67_p, -- Diff_p clock buffer input IB => lv67_n-- Diff_n clock buffer input ); IBUFGDS_sctn_se_inst : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => true, IBUF_DELAY_VALUE => "0", IOSTANDARD => "LVDS_25") port map ( O => SCTN, -- Clock buffer output I => lv69_p, -- Diff_p clock buffer input IB => lv69_n-- Diff_n clock buffer input ); FDCPE_sctn_inst : FDCPE generic map ( INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => SCTN_L1, -- Data output C => clk_165, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- Asynchronous clear input D => SCTN, --SCTN, -- Data input PRE => '0' -- Asynchronous set input ); ----- clk165_inst : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => true, IBUF_DELAY_VALUE => "0", IOSTANDARD => "LVDS_25") port map ( O => WRCLK_sig,--clklocal, -- Clock buffer output I => mgtck3_p, -- Diff_p clock buffer input IB => mgtck3_n-- Diff_n clock buffer input ); ---------------------------------------------- DCM_BASE_inst : DCM_BASE generic map ( CLKDV_DIVIDE => 3.0, --7.0,to improve acqisition properly modified on 02222008 7.5, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 6.0, -- Specify period of input clock in ns from 1.25 to 1000.00 CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "HIGH", -- LOW or HIGH frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "HIGH", -- LOW, HIGH, or HIGH_SER frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE port map ( CLK0 => WRCLK1_sig, -- 0 degree DCM CLK ouptput CLK180 => OPEN, -- 180 degree DCM CLK output CLK270 => OPEN, -- 270 degree DCM CLK output CLK2X => OPEN, -- 2X DCM CLK output CLK2X180 => OPEN, -- 2X, 180 degree DCM CLK out CLK90 => OPEN, -- 90 degree DCM CLK output CLKDV => RDCLK, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => OPEN, -- DCM CLK synthesis out (M/D) CLKFX180 => OPEN, -- 180 degree CLK synthesis out LOCKED => OPEN, -- DCM LOCK status output CLKFB => RDCLK_sig, -- DCM clock feedback CLKIN => WRCLK_sig,--tile0_clkdet_i, -- Clock input (from IBUFG, BUFG or DCM) RST => '0'--RESET --'0' --RST -- DCM asynchronous reset input ); --gtp_reset <= mgtreset; example_mgt_top_i : EXAMPLE_MGT_TOP generic map ( EXAMPLE_SIM_GTPRESET_SPEEDUP => 1, -- Speedup is turned on for simulation EXAMPLE_SIM_PLL_PERDIV2 => x"190", -- Set to the VCO Unit Interval time EXAMPLE_USE_CHIPSCOPE => 0 --1 - use chipscope to drive resets, --0 - drive resets from top level ports ) port map ( TILE0_REFCLK_PAD_N_IN => MGTREFCLKN_112, TILE0_REFCLK_PAD_P_IN => MGTREFCLKP_112, TILE1_REFCLK_PAD_N_IN => MGTREFCLKN_116, TILE1_REFCLK_PAD_P_IN => MGTREFCLKP_116, GTPRESET_IN => mgtreset, TILE0_PLLLKDET_OUT => tile0_plllkdet_i, TILE1_PLLLKDET_OUT => tile1_plllkdet_i, TILE0_CLKDET_OUT => tile0_clkdet_i, TILE1_CLKDET_OUT => tile1_clkdet_i, GTP_SYSTEM_RESET => system_reset, TILE0_RXCLK0_OUT => tile0_rxclk0_i, TILE0_RXCLK1_OUT => tile0_rxclk1_i, TILE1_RXCLK0_OUT => tile1_rxclk0_i, TILE0_RXDATA0_OUT => tile0_rxdata0_i, TILE0_RXDATA1_OUT => tile0_rxdata1_i, TILE1_RXDATA0_OUT => tile1_rxdata0_i, TILE1_RXDATA1_OUT => tile1_rxdata1_i, RXN_IN => rxn_in_i, RXP_IN => rxp_in_i, TXN_OUT => txn_out_i, TXP_OUT => txp_out_i, tile0_txcharisk0_i => tile0_txcharisk0_i, tile0_txcharisk1_i => tile0_txcharisk1_i, tile1_txcharisk0_i => tile1_txcharisk0_i, tile1_txcharisk1_i => tile1_txcharisk1_i, tile0_txdata0_i => tile0_txdata0_i, tile0_txdata1_i => tile0_txdata1_i, tile1_txdata0_i => tile1_txdata0_i, tile1_txdata1_i => tile1_txdata1_i, CLK_125 => CLK_125, tile0_rxcharisk0_i => tile0_rxcharisk0_i, tile0_rxcharisk1_i => tile0_rxcharisk1_i, tile1_rxcharisk0_i => tile1_rxcharisk0_i, tile1_rxcharisk1_i => tile1_rxcharisk1_i ); MGTTXP0_112 <= txp_out_i(0); MGTTXN0_112 <= txn_out_i(0); rxp_in_i(0) <= MGTRXP0_112; rxn_in_i(0) <= MGTRXN0_112; rxn_in_i(1) <= MGTRXN1_112; rxp_in_i(1) <= MGTRXP1_112; MGTTXN1_112 <= txn_out_i(1); MGTTXP1_112 <= txp_out_i(1); MGTTXP0_116 <= txp_out_i(2); MGTTXN0_116 <= txn_out_i(2); rxp_in_i(2) <= MGTRXP0_116; rxn_in_i(2) <= MGTRXN0_116; rxn_in_i(3) <= MGTRXN1_116; rxp_in_i(3) <= MGTRXP1_116; MGTTXN1_116 <= txn_out_i(3); MGTTXP1_116 <= txp_out_i(3); rdclk_latch : BUFG port map ( O => RDCLK_sig, -- Clock buffer output I => WRCLK1_sig -- Clock buffer input ); WRCLK <= RDCLK_sig; ------------------------------------------------------------------- ------ 2008-09-26 -- Commented for reconfiguring test due to DRP--- ------ 2008-10-13 -- Commented once again for long run test of optical receiver block--- -- SYSMON_inst : SYSMON -- generic map ( -- INIT_40 => X"3000", -- Configuration register 0 -- INIT_41 => X"203D", -- Configuration register 1 -- INIT_42 => X"0A00", -- Configuration register 2 -- INIT_43 => X"0000", -- Test register 0 -- INIT_44 => X"0000", -- Test register 1 -- INIT_45 => X"0000", -- Test register 2 -- INIT_46 => X"0000", -- Test register 3 -- INIT_47 => X"0000", -- Test register 4 -- INIT_48 => X"0101", -- Sequence register 0 -- INIT_49 => X"0000", -- Sequence register 1 -- INIT_4A => X"0100", -- Sequence register 2 -- INIT_4B => X"0000", -- Sequence register 3 -- INIT_4C => X"0000", -- Sequence register 4 -- INIT_4D => X"0000", -- Sequence register 5 -- INIT_4E => X"0000", -- Sequence register 6 -- INIT_4F => X"0000", -- Sequence register 7 -- INIT_50 => X"FEB9", -- Alarm limit register 0 -- INIT_51 => X"0000", -- Alarm limit register 1 -- INIT_52 => X"0000", -- Alarm limit register 2 -- INIT_53 => X"0000", -- Alarm limit register 3 -- INIT_54 => X"FE2A", -- Alarm limit register 4 -- INIT_55 => X"0000", -- Alarm limit register 5 -- INIT_56 => X"0000", -- Alarm limit register 6 -- INIT_57 => X"0000", -- Alarm limit register 7 -- SIM_MONITOR_FILE => "design.txt") -- Simulation analog entry file -- port map ( -- ALM => ALM, -- 3-bit output for temp, Vccint and Vccaux -- BUSY => BUSY, -- 1-bit output ADC busy signal -- CHANNEL => CHANNEL, -- 5-bit output channel selection -- DO => DO, -- 16-bit output data bus for dynamic reconfig -- DRDY => DRDY, -- 1-bit output data ready for dynamic reconfig -- -- EOC => EOC, -- 1-bit output end of conversion -- EOS => EOS, -- 1-bit output end of sequence -- -- JTAGBUSY => JTAGBUSY, -- 1-bit output JTAG DRP busy -- -- JTAGLOCKED => JTAGLOCKED, -- 1-bit output DRP port lock -- -- JTAGMODIFIED => JTAGMODIFIED, -- 1-bit output JTAG write to DRP -- -- OT => OT, -- 1-bit output over temperature alarm -- CONVST => '0',--CONVST, -- 1-bit input convert start -- CONVSTCLK => '0',--CONVSTCLK, -- 1-bit input convert start clock -- DADDR => DADDR, -- 7-bit input address bus for dynamic reconfig -- DCLK => RDCLK, -- 1-bit input clock for dynamic reconfig -- DEN => EOS,--DEN, -- 1-bit input enable for dynamic reconfig -- DI => "0000000000000000",--DI, -- 16-bit input data bus for dynamic reconfig -- DWE => '0',--DWE, -- 1-bit input write enable for dynamic reconfig -- RESET => gtp_reset,--Added on 2008-10-15 '0',--RESET, --'0',--RESET, -- 1-bit input active high reset -- VAUXN => "0000000000000000",--VAUXN, -- 16-bit input N-side auxiliary analog input -- VAUXP => "0000000000000000",--VAUXP, -- 16-bit input P-side auxiliary analog input -- VN => '0',--VN, -- 1-bit input N-side analog input -- VP => '0'--VP) -- 1-bit input P-side analog input -- ); -- -- DADDR <= "00" & CHANNEL; -- read_reg <= "0000000000000000" & DO(15 downto 6) & check_flag; -- -- valid_regceb <= '0'; valid_data <= (others => '0'); --PACKETIZATION LOGIC TRANS_TEST: trans_test2 PORT MAP (clk_165 => clk_165, clk_125 => CLK_125, rst => rstin, sctn_in => SCTN_L1, valid_regceb => valid_regceb, valid_data => valid_data, usb_command => usb_command, usb_load => FIBRE_LOAD, ---Outputs dout1 => tile0_txdata0_i, dout2 => tile0_txdata1_i, dout3 => tile1_txdata0_i, dout4 => tile1_txdata1_i, charisk1 => tile0_txcharisk0_i, charisk2 => tile0_txcharisk1_i, charisk3 => tile1_txcharisk0_i, charisk4 => tile1_txcharisk1_i, ip_dpram_en => open ); t0_rxcharisk0 <= tile0_rxdata0_i(0); t0_rxcharisk1 <= tile0_rxdata0_i(1); t1_rxcharisk0 <= tile0_rxdata0_i(2); t1_rxcharisk1 <= tile0_rxdata0_i(3); t2_rxcharisk0 <= tile0_rxdata1_i(0); t2_rxcharisk1 <= tile0_rxdata1_i(1); t3_rxcharisk0 <= tile0_rxdata1_i(2); t3_rxcharisk1 <= tile0_rxdata1_i(3); t0_txcharisk0 <= FIBRE_LOAD; t0_txcharisk1 <= tile0_txcharisk0_i(1); t1_txcharisk0 <= tile0_txcharisk1_i(0); t1_txcharisk1 <= tile0_txcharisk1_i(1); t2_txcharisk0 <= tile1_txcharisk0_i(0); t2_txcharisk1 <= tile1_txcharisk0_i(1); t3_txcharisk0 <= tile1_txcharisk1_i(0); t3_txcharisk1 <= tile1_txcharisk1_i(1); mgtrst_out <= CLK_125; --------- DCM for the fifo_rd_clk fifo_clock_gen : fifo_clk_gen1 Port map ( clk_in => clk_165, reset_in => rstin, clk_out => USB_CLK, clk200 => clk200, lock_out => open ); -------- chip_sel <= "00"; usb_if_inst1 : usb_agfo1 Port map( CLK => USB_CLK, RESET_IN => rstin, U_WR_usb => WR, U_RD_usb => RD, U_ADDR => An, CHIP_SEL => chip_sel, U_DATA => Dn, READ_REG => read_reg, POL_SELECTION => open, PIPELINE_EN => open, OUTPUT_REG => usb_command, WALSH_WREN_out => open, WALSH_OPREG_LOAD => open, GAIN_WREN1_out => open, GAIN_WREN2_out => open, CHSEL_WREN_out => open, OPREG_LOAD_out => open, SER_WREN_out => open, SER_OPREG_LOAD => open, SCTN_WREN_out => open, SCTN_OPREG_LOAD => FIBRE_LOAD, EXTRST_WR_EN => open, RST_OPREG_LOAD => RST_LOAD, OPREG_RDEN => open ); end Behavioral;