AGFO_FIBRE_V1 Project Status
Project File: agfo_fibre_v1.ise Current State: Programming File Generated
Module Name: PACK_MGT_TOP_V1
  • Errors:
No Errors
Target Device: xc5vsx50t-1ff665
  • Warnings:
498 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Fri Mar 13 09:45:41 2009
 
AGFO_FIBRE_V1 Partition Summary
No partition information was found.
 
Device Utilization Summary
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,361 32,640 4%  
    Number used as Flip Flops 1,361      
Number of Slice LUTs 1,108 32,640 3%  
    Number used as logic 1,089 32,640 3%  
        Number using O6 output only 946      
        Number using O5 output only 133      
        Number using O5 and O6 10      
    Number used as Memory 9 12,480 1%  
        Number used as Shift Register 9      
            Number using O6 output only 9      
    Number used as exclusive route-thru 10      
Number of route-thrus 144 65,280 1%  
    Number using O6 output only 143      
    Number using O5 output only 1      
Slice Logic Distribution     
Number of occupied Slices 780 8,160 9%  
Number of LUT Flip Flop pairs used 1,939      
    Number with an unused Flip Flop 578 1,939 29%  
    Number with an unused LUT 831 1,939 42%  
    Number of fully used LUT-FF pairs 530 1,939 27%  
    Number of unique control sets 100      
IO Utilization     
Number of bonded IOBs 39 360 10%  
Specific Feature Utilization     
Number of BlockRAM/FIFO 18 132 13%  
    Number using BlockRAM only 18      
Total primitives used     
        Number of 36k BlockRAM used 16      
        Number of 18k BlockRAM used 4      
Total Memory used (KB) 648 4,752 13%  
Number of BUFG/BUFGCTRLs 21 32 65%  
    Number used as BUFGs 21      
Number of BUFDSs 2 6 33%  
Number of DCM_ADVs 5 12 41%  
Number of GTP_DUALs 2 6 33%  
Number of PLL_ADVs 2 6 33%  
Total equivalent gate count for design 2,413,848      
Additional JTAG gate count for IOBs 2,832      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Mar 12 16:34:43 20090487 Warnings56 Infos
Translation ReportCurrentThu Mar 12 16:34:56 2009004 Infos
Map ReportCurrentThu Mar 12 16:39:00 200905 Warnings11 Infos
Place and Route ReportCurrentThu Mar 12 16:39:48 200903 Warnings2 Infos
Static Timing ReportCurrentThu Mar 12 16:40:12 2009002 Infos
Bitgen ReportCurrentThu Mar 12 16:41:34 200903 Warnings0