-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:13:09 05/05/2009 -- Design Name: AGFO_FIBRE_V4_SX -- Module Name: D:/MWA_AGFOFIBRE_SIM_FEB08/MWA_FIBER_SX/agfo_fibre_sx_v4/TB1_V4_SX.vhd -- Project Name: agfo_fibre_sx_v4 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: AGFO_FIBRE_V4_SX -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; library STD; use std.textio.all; library work; use work.classio.all; ENTITY TB1_V5_SX_vhd IS END TB1_V5_SX_vhd; ARCHITECTURE behavior OF TB1_V5_SX_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT AGFO_FIBRE_V5_SX PORT( lv67_p : IN std_logic; lv67_n : IN std_logic; lv69_p : IN std_logic; lv69_n : IN std_logic; An : IN std_logic_vector(7 downto 0); WR : IN std_logic; RD : IN std_logic; ADFB_DAT_A1_P : IN std_logic_vector(4 downto 0); ADFB_DAT_A1_N : IN std_logic_vector(4 downto 0); ADFB_DAT_B1_P : IN std_logic_vector(4 downto 0); ADFB_DAT_B1_N : IN std_logic_vector(4 downto 0); ADFB_DAT_C1_P : IN std_logic_vector(4 downto 0); ADFB_DAT_C1_N : IN std_logic_vector(4 downto 0); ADFB_DAT_D1_P : IN std_logic_vector(4 downto 0); ADFB_DAT_D1_N : IN std_logic_vector(4 downto 0); ADFB_DAT_A2_P : IN std_logic_vector(4 downto 0); ADFB_DAT_A2_N : IN std_logic_vector(4 downto 0); ADFB_DAT_B2_P : IN std_logic_vector(4 downto 0); ADFB_DAT_B2_N : IN std_logic_vector(4 downto 0); ADFB_DAT_C2_P : IN std_logic_vector(4 downto 0); ADFB_DAT_C2_N : IN std_logic_vector(4 downto 0); ADFB_DAT_D2_P : IN std_logic_vector(4 downto 0); ADFB_DAT_D2_N : IN std_logic_vector(4 downto 0); DATA_READY_A1_P : IN std_logic; DATA_READY_A1_N : IN std_logic; DATA_READY_B1_P : IN std_logic; DATA_READY_B1_N : IN std_logic; DATA_READY_C1_P : IN std_logic; DATA_READY_C1_N : IN std_logic; DATA_READY_D1_P : IN std_logic; DATA_READY_D1_N : IN std_logic; DATA_READY_A2_P : IN std_logic; DATA_READY_A2_N : IN std_logic; DATA_READY_B2_P : IN std_logic; DATA_READY_B2_N : IN std_logic; DATA_READY_C2_P : IN std_logic; DATA_READY_C2_N : IN std_logic; DATA_READY_D2_P : IN std_logic; DATA_READY_D2_N : IN std_logic; ADFB_CLK_A1_P : IN std_logic; ADFB_CLK_A1_N : IN std_logic; ADFB_CLK_B1_P : IN std_logic; ADFB_CLK_B1_N : IN std_logic; ADFB_CLK_C1_P : IN std_logic; ADFB_CLK_C1_N : IN std_logic; ADFB_CLK_D1_P : IN std_logic; ADFB_CLK_D1_N : IN std_logic; ADFB_CLK_A2_P : IN std_logic; ADFB_CLK_A2_N : IN std_logic; ADFB_CLK_B2_P : IN std_logic; ADFB_CLK_B2_N : IN std_logic; ADFB_CLK_C2_P : IN std_logic; ADFB_CLK_C2_N : IN std_logic; ADFB_CLK_D2_P : IN std_logic; ADFB_CLK_D2_N : IN std_logic; -- mgtck3_n : IN std_logic; -- mgtck3_p : IN std_logic; MGTRXP0_112 : IN std_logic; MGTRXN0_112 : IN std_logic; MGTRXN1_112 : IN std_logic; MGTRXP1_112 : IN std_logic; MGTREFCLKP_112 : IN std_logic; MGTREFCLKN_112 : IN std_logic; MGTRXP0_116 : IN std_logic; MGTRXN0_116 : IN std_logic; MGTRXN1_116 : IN std_logic; MGTRXP1_116 : IN std_logic; MGTREFCLKP_116 : IN std_logic; MGTREFCLKN_116 : IN std_logic; Dn : INOUT std_logic_vector(7 downto 0); led1 : OUT std_logic; led2 : OUT std_logic; led3 : OUT std_logic; led4 : OUT std_logic; led5 : OUT std_logic; led6 : OUT std_logic; led7 : OUT std_logic; led8 : OUT std_logic; led9 : OUT std_logic; led10 : OUT std_logic; led11 : OUT std_logic; led12 : OUT std_logic; gc8_p : OUT std_logic; gc8_n : OUT std_logic; extck2_p : OUT std_logic; extck2_n : OUT std_logic; DAS_OP_P : OUT std_logic_vector(9 downto 0); DAS_OP_N : OUT std_logic_vector(9 downto 0); DAS_trigger_P : OUT std_logic; DAS_trigger_N : OUT std_logic; DAS_clk_P : OUT std_logic; DAS_clk_N : OUT std_logic; DAS_pvalid_P : OUT std_logic; DAS_pvalid_N : OUT std_logic; MGTTXP0_112 : OUT std_logic; MGTTXN0_112 : OUT std_logic; MGTTXN1_112 : OUT std_logic; MGTTXP1_112 : OUT std_logic; MGTTXP0_116 : OUT std_logic; MGTTXN0_116 : OUT std_logic; MGTTXN1_116 : OUT std_logic; MGTTXP1_116 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL lv67_p : std_logic := '0'; SIGNAL lv67_n : std_logic := '0'; SIGNAL lv69_p : std_logic := '0'; SIGNAL lv69_n : std_logic := '0'; SIGNAL WR : std_logic := '0'; SIGNAL RD : std_logic := '0'; SIGNAL DATA_READY_A1_P : std_logic := '0'; SIGNAL DATA_READY_A1_N : std_logic := '0'; SIGNAL DATA_READY_B1_P : std_logic := '0'; SIGNAL DATA_READY_B1_N : std_logic := '0'; SIGNAL DATA_READY_C1_P : std_logic := '0'; SIGNAL DATA_READY_C1_N : std_logic := '0'; SIGNAL DATA_READY_D1_P : std_logic := '0'; SIGNAL DATA_READY_D1_N : std_logic := '0'; SIGNAL DATA_READY_A2_P : std_logic := '0'; SIGNAL DATA_READY_A2_N : std_logic := '0'; SIGNAL DATA_READY_B2_P : std_logic := '0'; SIGNAL DATA_READY_B2_N : std_logic := '0'; SIGNAL DATA_READY_C2_P : std_logic := '0'; SIGNAL DATA_READY_C2_N : std_logic := '0'; SIGNAL DATA_READY_D2_P : std_logic := '0'; SIGNAL DATA_READY_D2_N : std_logic := '0'; SIGNAL ADFB_CLK_A1_P : std_logic := '0'; SIGNAL ADFB_CLK_A1_N : std_logic := '0'; SIGNAL ADFB_CLK_B1_P : std_logic := '0'; SIGNAL ADFB_CLK_B1_N : std_logic := '0'; SIGNAL ADFB_CLK_C1_P : std_logic := '0'; SIGNAL ADFB_CLK_C1_N : std_logic := '0'; SIGNAL ADFB_CLK_D1_P : std_logic := '0'; SIGNAL ADFB_CLK_D1_N : std_logic := '0'; SIGNAL ADFB_CLK_A2_P : std_logic := '0'; SIGNAL ADFB_CLK_A2_N : std_logic := '0'; SIGNAL ADFB_CLK_B2_P : std_logic := '0'; SIGNAL ADFB_CLK_B2_N : std_logic := '0'; SIGNAL ADFB_CLK_C2_P : std_logic := '0'; SIGNAL ADFB_CLK_C2_N : std_logic := '0'; SIGNAL ADFB_CLK_D2_P : std_logic := '0'; SIGNAL ADFB_CLK_D2_N : std_logic := '0'; SIGNAL mgtck3_n : std_logic := '0'; SIGNAL mgtck3_p : std_logic := '0'; SIGNAL MGTRXP0_112 : std_logic := '0'; SIGNAL MGTRXN0_112 : std_logic := '0'; SIGNAL MGTRXN1_112 : std_logic := '0'; SIGNAL MGTRXP1_112 : std_logic := '0'; SIGNAL MGTREFCLKP_112 : std_logic := '0'; SIGNAL MGTREFCLKN_112 : std_logic := '0'; SIGNAL MGTRXP0_116 : std_logic := '0'; SIGNAL MGTRXN0_116 : std_logic := '0'; SIGNAL MGTRXN1_116 : std_logic := '0'; SIGNAL MGTRXP1_116 : std_logic := '0'; SIGNAL MGTREFCLKP_116 : std_logic := '0'; SIGNAL MGTREFCLKN_116 : std_logic := '0'; SIGNAL An : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_A1_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_A1_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_B1_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_B1_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_C1_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_C1_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_D1_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_D1_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_A2_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_A2_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_B2_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_B2_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_C2_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_C2_N : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_D2_P : std_logic_vector(4 downto 0) := (others=>'0'); SIGNAL ADFB_DAT_D2_N : std_logic_vector(4 downto 0) := (others=>'0'); --BiDirs SIGNAL Dn : std_logic_vector(7 downto 0); --Outputs SIGNAL led1 : std_logic; SIGNAL led2 : std_logic; SIGNAL led3 : std_logic; SIGNAL led4 : std_logic; SIGNAL led5 : std_logic; SIGNAL led6 : std_logic; SIGNAL led7 : std_logic; SIGNAL led8 : std_logic; SIGNAL led9 : std_logic; SIGNAL led10 : std_logic; SIGNAL led11 : std_logic; SIGNAL led12 : std_logic; SIGNAL gc8_p : std_logic; SIGNAL gc8_n : std_logic; SIGNAL extck2_p : std_logic; SIGNAL extck2_n : std_logic; SIGNAL DAS_OP_P : std_logic_vector(9 downto 0); SIGNAL DAS_OP_N : std_logic_vector(9 downto 0); SIGNAL DAS_trigger_P : std_logic; SIGNAL DAS_trigger_N : std_logic; SIGNAL DAS_clk_P : std_logic; SIGNAL DAS_clk_N : std_logic; SIGNAL DAS_pvalid_P : std_logic; SIGNAL DAS_pvalid_N : std_logic; SIGNAL MGTTXP0_112 : std_logic; SIGNAL MGTTXN0_112 : std_logic; SIGNAL MGTTXN1_112 : std_logic; SIGNAL MGTTXP1_112 : std_logic; SIGNAL MGTTXP0_116 : std_logic; SIGNAL MGTTXN0_116 : std_logic; SIGNAL MGTTXN1_116 : std_logic; SIGNAL MGTTXP1_116 : std_logic; SIGNAL clk165,clk125,clk_330MHz : std_logic; SIGNAL sctn_in ,rstin,RESET,mgt_reset: std_logic := '0'; component SIM_RESET_MGT_MODEL port ( GSR_IN : in std_logic ); end component; SIGNAL c1 : std_logic_vector(9 downto 0):=(others => '0'); SIGNAL sctn_counter1 : std_logic_vector(23 downto 0):=(others => '0'); --FOR USB MODULE SIGNAL USB_CLK : STD_LOGIC; --:='0'; SIGNAL t1_uaddr : std_logic_vector(1 downto 0); SIGNAL t2_uaddr : std_logic; SIGNAL t3_uaddr : std_logic_vector(4 downto 0):=(OTHERS => '0'); SIGNAL counter : std_logic_vector(15 downto 0):=(OTHERS => '0'); SIGNAL st : std_logic_vector(4 downto 0):=(OTHERS => '0'); SIGNAL COMMAND : std_logic_vector(4 downto 0); SIGNAL DATA: std_logic_vector(7 downto 0); SIGNAL inc_st,resetst,RST_CTR,INC_STATE1,LOAD_DATA,INC_CH_CTR,chsel_done,START_WRITING: std_logic := '0'; SIGNAL START_COUNTER,START_COUNTER1,START_DONE,INC_GAIN_CTR,POL1_DONE,POL2_DONE: std_logic := '0'; SIGNAL INT_STATE_CTR ,INT_STATE_CTR1: STD_LOGIC_VECTOR( 3 DOWNTO 0):=(OTHERS => '0'); SIGNAL STATE_CTR1 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (OTHERS => '0'); SIGNAL CH_CTR : STD_LOGIC_VECTOR(5 DOWNTO 0):=(OTHERS => '0'); SIGNAL CH_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):=(OTHERS => '0'); SIGNAL DONE1,DONE2,DONE3,DONE3a,DONE3b,USB_OP_COMPLETE,USB_OP_COMPLETE1: STD_LOGIC:='0'; SIGNAL P1_DONE,P2_DONE,INC_RAMP_CTR,LOAD_RDATA,DONE2aa : STD_LOGIC:='0'; SIGNAL ctra,dummyctra : std_logic_vector(31 downto 0) := X"00000000"; SIGNAL sclk : std_logic_vector( 1 downto 0); SIGNAL m_dr : std_logic_vector( 1 downto 0); SIGNAL sdata : std_logic_vector( 4 downto 0); signal gp_lines : std_logic_vector(7 downto 0); signal t0_txcharisk0: std_logic_vector(1 downto 0); signal t0_txcharisk1: std_logic_vector(1 downto 0); signal t1_txcharisk0: std_logic_vector(1 downto 0); signal t1_txcharisk1: std_logic_vector(1 downto 0); signal t0_rxcharisk0: std_logic_vector(1 downto 0); signal t0_rxcharisk1: std_logic_vector(1 downto 0); signal t1_rxcharisk0: std_logic_vector(1 downto 0); signal t1_rxcharisk1: std_logic_vector(1 downto 0); signal nu1,nu2,nu3,nu4: std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: AGFO_FIBRE_V5_SX PORT MAP( lv67_p => lv67_p, lv67_n => lv67_n, lv69_p => lv69_p, lv69_n => lv69_n, led1 => led1, led2 => led2, led3 => led3, led4 => led4, led5 => led5, led6 => led6, led7 => led7, led8 => led8, led9 => led9, led10 => led10, led11 => led11, led12 => led12, An => An, Dn => Dn, WR => WR, RD => RD, gc8_p => gc8_p, gc8_n => gc8_n, extck2_p => extck2_p, extck2_n => extck2_n, ADFB_DAT_A1_P => ADFB_DAT_A1_P, ADFB_DAT_A1_N => ADFB_DAT_A1_N, ADFB_DAT_B1_P => ADFB_DAT_B1_P, ADFB_DAT_B1_N => ADFB_DAT_B1_N, ADFB_DAT_C1_P => ADFB_DAT_C1_P, ADFB_DAT_C1_N => ADFB_DAT_C1_N, ADFB_DAT_D1_P => ADFB_DAT_D1_P, ADFB_DAT_D1_N => ADFB_DAT_D1_N, ADFB_DAT_A2_P => ADFB_DAT_A2_P, ADFB_DAT_A2_N => ADFB_DAT_A2_N, ADFB_DAT_B2_P => ADFB_DAT_B2_P, ADFB_DAT_B2_N => ADFB_DAT_B2_N, ADFB_DAT_C2_P => ADFB_DAT_C2_P, ADFB_DAT_C2_N => ADFB_DAT_C2_N, ADFB_DAT_D2_P => ADFB_DAT_D2_P, ADFB_DAT_D2_N => ADFB_DAT_D2_N, DATA_READY_A1_P => DATA_READY_A1_P, DATA_READY_A1_N => DATA_READY_A1_N, DATA_READY_B1_P => DATA_READY_B1_P, DATA_READY_B1_N => DATA_READY_B1_N, DATA_READY_C1_P => DATA_READY_C1_P, DATA_READY_C1_N => DATA_READY_C1_N, DATA_READY_D1_P => DATA_READY_D1_P, DATA_READY_D1_N => DATA_READY_D1_N, DATA_READY_A2_P => DATA_READY_A2_P, DATA_READY_A2_N => DATA_READY_A2_N, DATA_READY_B2_P => DATA_READY_B2_P, DATA_READY_B2_N => DATA_READY_B2_N, DATA_READY_C2_P => DATA_READY_C2_P, DATA_READY_C2_N => DATA_READY_C2_N, DATA_READY_D2_P => DATA_READY_D2_P, DATA_READY_D2_N => DATA_READY_D2_N, ADFB_CLK_A1_P => ADFB_CLK_A1_P, ADFB_CLK_A1_N => ADFB_CLK_A1_N, ADFB_CLK_B1_P => ADFB_CLK_B1_P, ADFB_CLK_B1_N => ADFB_CLK_B1_N, ADFB_CLK_C1_P => ADFB_CLK_C1_P, ADFB_CLK_C1_N => ADFB_CLK_C1_N, ADFB_CLK_D1_P => ADFB_CLK_D1_P, ADFB_CLK_D1_N => ADFB_CLK_D1_N, ADFB_CLK_A2_P => ADFB_CLK_A2_P, ADFB_CLK_A2_N => ADFB_CLK_A2_N, ADFB_CLK_B2_P => ADFB_CLK_B2_P, ADFB_CLK_B2_N => ADFB_CLK_B2_N, ADFB_CLK_C2_P => ADFB_CLK_C2_P, ADFB_CLK_C2_N => ADFB_CLK_C2_N, ADFB_CLK_D2_P => ADFB_CLK_D2_P, ADFB_CLK_D2_N => ADFB_CLK_D2_N, DAS_OP_P => DAS_OP_P, DAS_OP_N => DAS_OP_N, DAS_trigger_P => DAS_trigger_P, DAS_trigger_N => DAS_trigger_N, DAS_clk_P => DAS_clk_P, DAS_clk_N => DAS_clk_N, DAS_pvalid_P => DAS_pvalid_P, DAS_pvalid_N => DAS_pvalid_N, -- mgtck3_n => mgtck3_n, -- mgtck3_p => mgtck3_p, MGTTXP0_112 => MGTTXP0_112, MGTTXN0_112 => MGTTXN0_112, MGTRXP0_112 => MGTRXP0_112, MGTRXN0_112 => MGTRXN0_112, MGTRXN1_112 => MGTRXN1_112, MGTRXP1_112 => MGTRXP1_112, MGTTXN1_112 => MGTTXN1_112, MGTTXP1_112 => MGTTXP1_112, MGTREFCLKP_112 => MGTREFCLKP_112, MGTREFCLKN_112 => MGTREFCLKN_112, MGTTXP0_116 => MGTTXP0_116, MGTTXN0_116 => MGTTXN0_116, MGTRXP0_116 => MGTRXP0_116, MGTRXN0_116 => MGTRXN0_116, MGTRXN1_116 => MGTRXN1_116, MGTRXP1_116 => MGTRXP1_116, MGTTXN1_116 => MGTTXN1_116, MGTTXP1_116 => MGTTXP1_116, MGTREFCLKP_116 => MGTREFCLKP_116, MGTREFCLKN_116 => MGTREFCLKN_116 ); RESET <= '0' , '1' AFTER 200 NS; mgt_reset <= '1', '0' after 200 ns; sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL port map ( GSR_IN => mgt_reset ); mgtck3_p <= clk125; mgtck3_n <= not clk125; -- lv67_p <= clk165; lv67_n <= not lv67_p; lv69_p <= sctn_in; lv69_n <= not lv69_p; MGTREFCLKP_112 <= clk125; MGTREFCLKN_112 <= not clk125; MGTREFCLKP_112 <= clk125; MGTREFCLKN_112 <= not clk125; MGTRXP0_112 <= MGTTXP0_112; MGTRXN0_112 <= MGTTXN0_112; MGTRXN1_112 <= MGTTXN1_112; MGTRXP1_112 <= MGTTXP1_112; MGTREFCLKP_116 <= clk125; MGTREFCLKN_116 <= not clk125; MGTRXP0_116 <= MGTTXP0_116; MGTRXN0_116 <= MGTTXN0_116; MGTRXN1_116 <= MGTTXN1_116; MGTRXP1_116 <= MGTTXP1_116; clk_330: process -- Generate clock waveform of 330 MHz begin clk_330MHz<= '1', '0' after 1.5 ns, '1' after 3 ns, '0' after 4.5 ns; wait for 6 ns ; end process clk_330; clk_125: process -- Generate clock waveform of 330 MHz begin clk125<= '1', '0' after 4 ns, '1' after 8 ns, '0' after 12 ns; wait for 16 ns ; end process clk_125; clk_165: process -- Generate clock waveform of 330 MHz begin clk165<= '1', '0' after 3 ns, '1' after 6 ns, '0' after 9 ns; wait for 12 ns ; end process clk_165; SCTN_p: process(clk165) -- generate clock waveform begin if clk165'event and clk165 = '1' then sctn_counter1 <= sctn_counter1 + '1'; sctn_in <= '1'; if sctn_counter1 = 32767 then --8388608 then sctn_in <= '0'; sctn_counter1 <= (others => '0'); end if; end if; end process SCTN_p; --============================================================================================== t1_uaddr<= "00"; t3_uaddr<= COMMAND; --"0001";--"0001";--"0000"; An <= t3_uaddr & t2_uaddr & t1_uaddr; Dn <= DATA; USB_CLKp: process -- generate clock waveform begin USB_CLK <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns; wait for 400 ns ; end process USB_CLKp; process(RESET,USB_CLK) begin if USB_CLK'event and USB_CLK = '1' then if RESET = '0' then st <= (others => '0'); elsif inc_st = '1' then st <= st + '1'; end if; end if; end process; PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF RESET = '0' THEN COMMAND <= (OTHERS=>'0'); WR <= '0'; START_COUNTER <= '0'; INC_GAIN_CTR <= '0'; POL1_DONE <= '0'; POL2_DONE <= '0'; t2_uaddr<= '0'; resetst <= '0'; inc_st<= '0'; RST_CTR<= '0'; START_COUNTER1 <= '0'; LOAD_DATA <= '0'; chsel_done <= '0'; DONE1 <= '0'; DONE2 <= '0'; DONE2aa<= '0'; DONE3 <= '0'; DONE3a <= '0'; DONE3b <= '0'; USB_OP_COMPLETE <= '0'; P1_DONE <= '0'; P2_DONE <= '0'; INC_RAMP_CTR <= '0'; LOAD_RDATA <= '0'; ELSE CASE st IS WHEN "00000" => COMMAND <= "00000"; WR <= '0'; inc_st <= '1'; WHEN "00001" => WR <= '1'; inc_st <= '1'; WHEN "00010" => WR <= '1'; inc_st <= '1'; WHEN "00011" => WR <= '1'; inc_st <= '1'; WHEN "00100" => WR <= '1'; inc_st <= '1'; WHEN "00101" => WR <= '0'; inc_st <= '0'; START_COUNTER <= '1'; WHEN "00110" => -- WALSH REGISTER IF INT_STATE_CTR = 0 THEN COMMAND <= "00001"; DATA <= (OTHERS => '0'); WR <= '1'; inc_st <= '0'; ELSIF INT_STATE_CTR = 1 THEN COMMAND <= "00001"; DATA <= (OTHERS => '0'); WR <= '0'; -- USB_OP_COMPLETE <= '1'; ELSIF INT_STATE_CTR = 2 THEN DATA <= X"01"; WR <= '1'; ELSIF INT_STATE_CTR = 3 THEN DATA <= X"01"; WR <= '0'; ELSIF INT_STATE_CTR = 4 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR = 5 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR = 6 THEN DATA <= X"FF"; WR <= '1'; ELSIF INT_STATE_CTR = 7 THEN DATA <= X"FF"; WR <= '0'; ELSIF INT_STATE_CTR = 8 THEN DATA <= X"FF"; WR <= '1'; START_COUNTER <= '0'; ELSIF INT_STATE_CTR = 9 THEN DATA <= X"FF"; WR <= '0'; START_COUNTER <= '0'; inc_st <= '1'; t2_uaddr<= '0'; END IF; WHEN "00111" => -- fiber REGISTER IF STATE_CTR1 = 0 THEN -- 24 channels enabled WR <= '1'; COMMAND <= "00010"; inc_st <= '0'; INC_STATE1 <= '1'; DATA <= X"07"; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00010"; WR <= '0'; INC_STATE1 <= '0'; DATA <= X"07"; ELSIF STATE_CTR1 = 2 AND DONE2aa = '0' THEN START_COUNTER1<= '1'; IF INT_STATE_CTR1 = 0 THEN DATA <= X"00"; WR <= '1'; INC_STATE1 <= '0'; ELSIF INT_STATE_CTR1 = 1 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR1 = 2 THEN DATA <= X"05"; WR <= '1'; ELSIF INT_STATE_CTR1 = 3 THEN DATA <= X"05"; WR <= '0'; ELSIF INT_STATE_CTR1 = 4 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR1 = 5 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR1 = 6 THEN DATA <= X"00"; WR <= '1'; RST_CTR <= '1'; ELSIF INT_STATE_CTR1 = 7 THEN DATA <= X"00"; WR <= '0'; INC_CH_CTR <= '0'; START_COUNTER1 <= '0'; RST_CTR <= '0'; DONE2aa <= '1'; inc_st <= '1'; END IF; END IF; -- WHEN "00111" => -- IF t2_uaddr = '0' AND POL1_DONE = '0' then -- READ_DATA <= READ_DATA1; -- ELSIF t2_uaddr = '1' AND POL1_DONE = '1' then -- READ_DATA <= READ_DATA2; -- END IF; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00010"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= READ_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00010"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_GAIN_CTR <= '1'; -- DATA <= READ_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND POL2_DONE = '0' THEN -- START_COUNTER1<= '1'; -- -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= READ_DATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_GAIN_CTR <= '0'; ---- START_COUNTER1<= '1'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= READ_DATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= READ_DATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=READ_DATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= READ_DATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= READ_DATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= READ_DATA(31 downto 24); -- WR <= '1'; -- INC_GAIN_CTR <= '1'; -- IF GAIN_CTR = 256 THEN -- RST_CTR <= '1'; -- END IF; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= READ_DATA(31 downto 24); -- WR <= '0'; -- INC_GAIN_CTR <= '0'; -- START_COUNTER1 <= '0'; -- IF GAIN_CTR = 128 THEN -- t2_uaddr<= '1'; -- END IF; -- IF GAIN_CTR = 128 THEN -- POL1_DONE <= '1'; -- END IF; -- -- IF GAIN_CTR = 127 THEN -- LOAD_DATA <= '1'; -- END IF; -- -- -- IF GAIN_CTR = 256 THEN -- INC_GAIN_CTR <= '0'; -- START_COUNTER1<= '0'; -- POL2_DONE <= '1'; -- inc_st <= '1'; -- t2_uaddr<= '0'; -- RST_CTR <= '0'; -- ---- ELSE ---- inc_st <= '0'; -- END IF; -- END IF; -- END IF; -- -- WHEN "01000" => -- inc_st <= '0'; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00011"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= CH_DATA(7 downto 0); -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00011"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_CH_CTR <= '1'; -- DATA <= CH_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND chsel_done = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= CH_DATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_CH_CTR <= '0'; ---- START_COUNTER1<= '1'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= CH_DATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= CH_DATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=CH_DATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= CH_DATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= CH_DATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= CH_DATA(31 downto 24); -- WR <= '1'; -- INC_CH_CTR <= '1'; -- IF CH_CTR = 33 THEN -- RST_CTR <= '1'; -- -- END IF; -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= CH_DATA(31 downto 24); -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- -- IF CH_CTR = 33 THEN -- t2_uaddr<= '1'; -- INC_CH_CTR <= '0'; -- START_COUNTER1<= '0'; -- inc_st <= '1'; -- chsel_done <= '1'; -- RST_CTR <= '0'; -- -- END IF; -- END IF; -- END IF; -- WHEN "01001" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00100"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"02"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00100"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"02"; -- -- ELSIF STATE_CTR1 = 2 AND DONE1 = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"02"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"02"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"02"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"02"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- START_COUNTER1 <= '0'; -- DONE1 <= '1'; -- RST_CTR <= '0'; -- inc_st <= '1'; -- -- -- END IF; -- END IF; ---------------------------------------------------------------------------- WHEN "01000" => -- SCTN REGISTER IF STATE_CTR1 = 0 THEN -- 24 channels enabled WR <= '1'; COMMAND <= "00101"; inc_st <= '0'; INC_STATE1 <= '1'; DATA <= X"FB"; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00101"; WR <= '0'; INC_STATE1 <= '0'; DATA <= X"FB"; ELSIF STATE_CTR1 = 2 AND DONE2 = '0' THEN START_COUNTER1<= '1'; IF INT_STATE_CTR1 = 0 THEN DATA <= X"FB"; WR <= '1'; INC_STATE1 <= '0'; ELSIF INT_STATE_CTR1 = 1 THEN DATA <= X"FB"; WR <= '0'; ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"0F"; -- DATA <= X"0F"; DATA <= X"8F"; WR <= '1'; ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"0F"; -- DATA <= X"0F"; DATA <= X"8F"; WR <= '0'; ELSIF INT_STATE_CTR1 = 4 THEN DATA <= X"3F"; WR <= '1'; ELSIF INT_STATE_CTR1 = 5 THEN DATA <= X"3F"; WR <= '0'; ELSIF INT_STATE_CTR1 = 6 THEN DATA <= X"17"; WR <= '1'; RST_CTR <= '1'; ELSIF INT_STATE_CTR1 = 7 THEN DATA <= X"17"; WR <= '0'; INC_CH_CTR <= '0'; START_COUNTER1 <= '0'; RST_CTR <= '0'; DONE2 <= '1'; inc_st <= '1'; END IF; END IF; WHEN "01001" => -- RESET REGISTER IF STATE_CTR1 = 0 THEN WR <= '1'; COMMAND <= "00110"; inc_st <= '0'; INC_STATE1 <= '1'; DATA <= X"78"; -- DATA <= X"07"; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00110"; WR <= '0'; INC_STATE1 <= '0'; DATA <= X"78"; -- DATA <= X"07"; ELSIF STATE_CTR1 = 2 AND DONE3 = '0' THEN START_COUNTER1<= '1'; IF INT_STATE_CTR1 = 0 THEN DATA <= X"78"; -- DATA <= X"07"; WR <= '1'; INC_STATE1 <= '0'; ELSIF INT_STATE_CTR1 = 1 THEN DATA <= X"78"; -- DATA <= X"07"; WR <= '0'; ELSIF INT_STATE_CTR1 = 2 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR1 = 3 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR1 = 4 THEN DATA <= X"01"; WR <= '1'; ELSIF INT_STATE_CTR1 = 5 THEN DATA <= X"01"; WR <= '0'; ELSIF INT_STATE_CTR1 = 6 THEN DATA <= X"01"; -- from fibre -- DATA <= X"00"; --from bkpln WR <= '1'; RST_CTR <= '1'; ELSIF INT_STATE_CTR1 = 7 THEN DATA <= X"01"; -- DATA <= X"00"; WR <= '0'; INC_CH_CTR <= '0'; START_COUNTER1 <= '0'; RST_CTR <= '0'; DONE3 <= '1'; inc_st <= '1'; USB_OP_COMPLETE <= '1'; END IF; END IF; ------------------------------------------------------------------------------------ -- WHEN "01100" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00110"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"00"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00110"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"00"; -- -- ELSIF STATE_CTR1 = 2 AND DONE3a = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"00"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- RST_CTR <= '0'; -- DONE3a <= '1'; -- inc_st <= '1'; -- -- -- END IF; -- END IF; -- -------------------------------------------------------------------------------------- -- WHEN "01101" => ---- IF t2_uaddr = '0' AND POL1_DONE = '0' then ---- READ_DATA <= READ_DATA1; ---- ELSIF t2_uaddr = '1' AND POL1_DONE = '1' then ---- READ_DATA <= READ_DATA2; ---- END IF; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00111"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= RAMPDATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00111"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_RAMP_CTR <= '1'; -- DATA <= RAMPDATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND P2_DONE = '0' THEN -- START_COUNTER1<= '1'; -- -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= RAMPDATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_RAMP_CTR <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= RAMPDATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= RAMPDATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=RAMPDATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= RAMPDATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= RAMPDATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= RAMPDATA(31 downto 24); -- WR <= '1'; -- INC_RAMP_CTR <= '1'; -- IF IPRAMP_CTR = 64 THEN -- RST_CTR <= '1'; -- END IF; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= RAMPDATA(31 downto 24); -- WR <= '0'; -- INC_RAMP_CTR <= '0'; -- START_COUNTER1 <= '0'; -- -- -- IF IPRAMP_CTR = 64 THEN -- INC_RAMP_CTR <= '0'; -- START_COUNTER1<= '0'; -- P2_DONE <= '1'; -- inc_st <= '1'; -- RST_CTR <= '0'; -- USB_OP_COMPLETE <= '1'; -- -- END IF; -- END IF; -- END IF; ------------------------------------------------------------------------------------ WHEN "10010" => --idle state IF STATE_CTR1 = 0 THEN WR <= '1'; COMMAND <= "00000"; inc_st <= '0'; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00000"; WR <= '0'; INC_STATE1 <= '0'; END IF; WHEN OTHERS => WR <= '0'; RD <= '0'; END CASE; END IF; END IF; END PROCESS; PROCESS(USB_CLK) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF START_COUNTER = '1' THEN INT_STATE_CTR <= INT_STATE_CTR + '1'; ELSE INT_STATE_CTR <= INT_STATE_CTR; END IF; IF INT_STATE_CTR = 9 THEN INT_STATE_CTR <= (OTHERS => '0'); END IF; END IF; END PROCESS; -------------------------------------------------------------------------- PROCESS(USB_CLK) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF INC_STATE1 = '1' THEN STATE_CTR1 <= STATE_CTR1 + '1'; ELSE STATE_CTR1 <= STATE_CTR1; END IF; IF RST_CTR = '1' THEN STATE_CTR1 <= (OTHERS => '0'); END IF; END IF; END PROCESS; PROCESS(USB_CLK) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF START_COUNTER1= '1' THEN INT_STATE_CTR1 <= INT_STATE_CTR1 + '1'; ELSE INT_STATE_CTR1 <= INT_STATE_CTR1; END IF; IF INT_STATE_CTR1 = 7 THEN INT_STATE_CTR1 <= (OTHERS => '0'); END IF; END IF; END PROCESS; --------------------------------------------------------- -- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_GAIN_CTR = '1' THEN -- GAIN_CTR <= GAIN_CTR + '1'; -- ELSE -- GAIN_CTR <= GAIN_CTR; -- END IF; -- -- IF GAIN_CTR = 257 THEN -- GAIN_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; ----------------------------------------------------------- -- -- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_CH_CTR = '1' THEN -- CH_CTR <= CH_CTR + '1'; -- ELSE -- CH_CTR <= CH_CTR; -- END IF; -- -- IF CH_CTR = 34 THEN --and P2_DONE = '1' THEN -- CH_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; -- --------------------------------------------------------- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_RAMP_CTR = '1' THEN -- IPRAMP_CTR <= IPRAMP_CTR + '1'; -- ELSE -- IPRAMP_CTR <= IPRAMP_CTR; -- END IF; -- -- IF IPRAMP_CTR = 65 then --AND P2_DONE = '1' THEN -- IPRAMP_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; --- Reading from the file for serial_pol-1 data ---------------- ADFB_CLK_A1_P <= NOT sclk(0); ADFB_CLK_A1_N <= sclk(0) ; --ADFB_CLK_A1_P; --ADFB_CLK_A1_P <= sclk(0); --ADFB_CLK_A1_N <= not ADFB_CLK_A1_P; --ADFB_CLK_B1_P <= sclk(0); --ADFB_CLK_B1_N <= not ADFB_CLK_B1_P; --ADFB_CLK_C1_P <= sclk(0); --ADFB_CLK_C1_N <= not ADFB_CLK_C1_P; --ADFB_CLK_D1_P <= sclk(0); --ADFB_CLK_D1_N <= not ADFB_CLK_D1_P; --ADFB_CLK_A2_P <= sclk(0); --ADFB_CLK_A2_N <= not ADFB_CLK_A2_P; --ADFB_CLK_B2_P <= sclk(0); --ADFB_CLK_B2_N <= not ADFB_CLK_B2_P; --ADFB_CLK_C2_P <= sclk(0); --ADFB_CLK_C2_N <= not ADFB_CLK_C2_P; --ADFB_CLK_D2_P <= sclk(0); --ADFB_CLK_D2_N <= not ADFB_CLK_D2_P; ADFB_CLK_B1_P <= NOT sclk(0); ADFB_CLK_B1_N <= sclk(0); ADFB_CLK_C1_P <= NOT sclk(0); ADFB_CLK_C1_N <= sclk(0) ; ADFB_CLK_D1_P <= NOT sclk(0); ADFB_CLK_D1_N <= sclk(0) ; ADFB_CLK_A2_P <= NOT sclk(0); ADFB_CLK_A2_N <= sclk(0) ; ADFB_CLK_B2_P <= NOT sclk(0); ADFB_CLK_B2_N <= sclk(0) ; ADFB_CLK_C2_P <= NOT sclk(0); ADFB_CLK_C2_N <= sclk(0) ; ADFB_CLK_D2_P <= NOT sclk(0); ADFB_CLK_D2_N <= sclk(0) ; file_read_process1: process(clk_330MHz) file infile0: TEXT is in "BKPLN_CLK_24ch.txt"; -- this is your input file name infile.txt. variable buf: line; variable CHECK0: std_logic_vector (1 downto 0); begin if clk_330MHz'event and clk_330MHz = '1' then read_vld (infile0, CHECK0); sclk <= CHECK0; end if; end process file_read_process1; ADFB_DAT_A1_P <= sdata; ADFB_DAT_A1_n <= not ADFB_DAT_A1_P; -- ADFB_DAT_B1_P(1 DOWNTO 0) <= sdata(1 DOWNTO 0); ADFB_DAT_B1_P(2) <= NOT sdata(2); ADFB_DAT_B1_P(4 DOWNTO 3) <= sdata(4 DOWNTO 3); ADFB_DAT_B1_N(1 DOWNTO 0) <= NOT sdata(1 DOWNTO 0); ADFB_DAT_B1_N(2) <= sdata(2); ADFB_DAT_B1_N(4 DOWNTO 3) <= NOT sdata(4 DOWNTO 3); --ADFB_DAT_B1_P <= sdata; --ADFB_DAT_B1_n <= not ADFB_DAT_B1_P; -- ADFB_DAT_C1_P(0) <= not sdata(0); ADFB_DAT_C1_P(1) <= not sdata(1); ADFB_DAT_C1_P(2) <= sdata(2); ADFB_DAT_C1_P(3) <= not sdata(3); ADFB_DAT_C1_P(4) <= sdata(4); ADFB_DAT_C1_N(0) <= sdata(0); ADFB_DAT_C1_N(1) <= sdata(1); ADFB_DAT_C1_N(2) <= not sdata(2); ADFB_DAT_C1_N(3) <= sdata(3); ADFB_DAT_C1_N(4) <= not sdata(4); ------------------------------------ --ADFB_DAT_C1_P <= sdata; --ADFB_DAT_C1_n <= not ADFB_DAT_C1_P; -- ADFB_DAT_D1_P(0) <= not sdata(0); ADFB_DAT_D1_P(1) <= sdata(1); ADFB_DAT_D1_P(2) <= not sdata(2); ADFB_DAT_D1_P(3) <= sdata(3); ADFB_DAT_D1_P(4) <= not sdata(4); ADFB_DAT_D1_N(0) <= sdata(0); ADFB_DAT_D1_N(1) <= NOT sdata(1); ADFB_DAT_D1_N(2) <= sdata(2); ADFB_DAT_D1_N(3) <= NOT sdata(3); ADFB_DAT_D1_N(4) <= sdata(4); --ADFB_DAT_D1_P <= sdata; --ADFB_DAT_D1_n <= not ADFB_DAT_D1_P; -- ADFB_DAT_A2_P <= sdata; ADFB_DAT_A2_n <= not ADFB_DAT_A2_P; ADFB_DAT_B2_P <= sdata; ADFB_DAT_B2_n <= not ADFB_DAT_B2_P; ADFB_DAT_C2_P <= sdata; ADFB_DAT_C2_n <= not ADFB_DAT_C2_P; ADFB_DAT_D2_P <= sdata; ADFB_DAT_D2_n <= not ADFB_DAT_D2_P; file_read_process2: process(clk_330MHz) file infile0: TEXT is in "BKPLN_DATA_24ch.TXT"; -- this is your input file name infile.txt. variable buf: line; variable CHECK1: std_logic_vector (4 downto 0); begin if clk_330MHz'event and clk_330MHz = '1' then read_vld5(infile0, CHECK1); sdata <= CHECK1; end if; end process file_read_process2; DATA_READY_A1_P <= m_dr(0); DATA_READY_A1_N <= not DATA_READY_A1_P; DATA_READY_B1_P <= m_dr(0); DATA_READY_B1_N <= not DATA_READY_B1_P; DATA_READY_C1_P <= not m_dr(0); --m_dr(0); DATA_READY_C1_N <= m_dr(0); --not DATA_READY_C1_P; DATA_READY_D1_P <= m_dr(0); DATA_READY_D1_N <= not DATA_READY_D1_P; DATA_READY_A2_P <= m_dr(0); DATA_READY_A2_N <= not DATA_READY_A2_P; DATA_READY_B2_P <= m_dr(0); DATA_READY_B2_N <= not DATA_READY_B2_P; DATA_READY_C2_P <= m_dr(0); DATA_READY_C2_N <= not DATA_READY_C2_P; DATA_READY_D2_P <= m_dr(0); DATA_READY_D2_N <= not DATA_READY_D2_P; file_read_process3: process(clk_330MHz) file infile0: TEXT is in "BKPLN_MUX_DATAR_24ch.TXT"; -- this is your input file name infile.txt. variable buf: line; variable CHECK0: std_logic_vector (1 downto 0); begin if clk_330MHz'event and clk_330MHz = '1' then read_vld (infile0, CHECK0); m_dr <= CHECK0; end if; end process file_read_process3; END;