---------------------------------------------------------------- -- Project : X14_AgFo_V6cp3_SX.ise -- File : X14_AgFo_V6cp3_SX.vhd -- Brought out Not in Table Flags from MGTS to RJ -- 5/8/2010 -- modified to incorporate delay module load pulse gen from USB -- includes checksum computation for usb interface - 14AUG09 -Vani/SM -- included files transtest2b and packetization codes modified by TP/Anish --at MIT during June 25-30, 2009 trip --In This version of the code , one of the mgt receiver is used.. -- This version of code includes TX and RX with actual DATA, SCTN and CLK -- from backplane.-- 6/5/09 /KPA/KSS/SM/AR ---------------------------------------------------------------- -- Project : agfo_vsib_chsel_V1.ise -- 03 march 2009--KPA -- Project : copied from agfo12_b3.ise/vhd -- 22/10/2008-RRI-RAL--KPA -- File : agfo_vsib_chsel_V1.vhd -- ----------------------------------------------------------------- -- Copied from agfo11_a and modified to receive CLK and SCTN from the BACKPLANE --################################################################################ -- Copied from agfo9_d directory after hardware testing. -- Channel selection and burstmode are restored in this -- project. -- Anish, March 22, 2008 -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity X14_AgFo_V6cp3_SX is Port ( lv67_p : in STD_LOGIC; -- GCLK IN lv67_n : in STD_LOGIC; lv69_p : in STD_LOGIC; -- SCTN IN lv69_n : in STD_LOGIC; led1 : out STD_LOGIC; led2 : out STD_LOGIC; led3 : out STD_LOGIC; led4 : out STD_LOGIC; led5 : out STD_LOGIC; led6 : out STD_LOGIC; led7 : out STD_LOGIC; led8 : out STD_LOGIC; led9 : out STD_LOGIC; led10 : out STD_LOGIC; led11 : out STD_LOGIC; led12 : out STD_LOGIC; An : in std_logic_vector(7 downto 0); Dn : inout std_logic_vector(7 downto 0); WR : in std_logic; RD : in std_logic; gc8_p :out std_logic; gc8_n :out std_logic; extck2_p:out std_logic; extck2_n:out std_logic; gc10_p :out std_logic; gc10_n :out std_logic; gc11_p :out std_logic; ADFB_DAT_A1_P : in std_logic_vector(4 downto 0); ADFB_DAT_A1_N : in std_logic_vector(4 downto 0); ADFB_DAT_B1_P : in std_logic_vector(4 downto 0); ADFB_DAT_B1_N : in std_logic_vector(4 downto 0); ADFB_DAT_C1_P : in std_logic_vector(4 downto 0); ADFB_DAT_C1_N : in std_logic_vector(4 downto 0); ADFB_DAT_D1_P : in std_logic_vector(4 downto 0); ADFB_DAT_D1_N : in std_logic_vector(4 downto 0); ADFB_DAT_A2_P : in std_logic_vector(4 downto 0); ADFB_DAT_A2_N : in std_logic_vector(4 downto 0); ADFB_DAT_B2_P : in std_logic_vector(4 downto 0); ADFB_DAT_B2_N : in std_logic_vector(4 downto 0); ADFB_DAT_C2_P : in std_logic_vector(4 downto 0); ADFB_DAT_C2_N : in std_logic_vector(4 downto 0); ADFB_DAT_D2_P : in std_logic_vector(4 downto 0); ADFB_DAT_D2_N : in std_logic_vector(4 downto 0); DATA_READY_A1_P : in std_logic; DATA_READY_A1_N : in std_logic; DATA_READY_B1_P : in std_logic; DATA_READY_B1_N : in std_logic; DATA_READY_C1_P : in std_logic; DATA_READY_C1_N : in std_logic; DATA_READY_D1_P : in std_logic; DATA_READY_D1_N : in std_logic; DATA_READY_A2_P : in std_logic; DATA_READY_A2_N : in std_logic; DATA_READY_B2_P : in std_logic; DATA_READY_B2_N : in std_logic; DATA_READY_C2_P : in std_logic; DATA_READY_C2_N : in std_logic; DATA_READY_D2_P : in std_logic; DATA_READY_D2_N : in std_logic; ADFB_CLK_A1_P : in std_logic; ADFB_CLK_A1_N : in std_logic; ADFB_CLK_B1_P : in std_logic; ADFB_CLK_B1_N : in std_logic; ADFB_CLK_C1_P : in std_logic; ADFB_CLK_C1_N : in std_logic; ADFB_CLK_D1_P : in std_logic; ADFB_CLK_D1_N : in std_logic; ADFB_CLK_A2_P : in std_logic; ADFB_CLK_A2_N : in std_logic; ADFB_CLK_B2_P : in std_logic; ADFB_CLK_B2_N : in std_logic; ADFB_CLK_C2_P : in std_logic; ADFB_CLK_C2_N : in std_logic; ADFB_CLK_D2_P : in std_logic; ADFB_CLK_D2_N : in std_logic; DAS_OP_P : out std_logic_vector(9 downto 0); DAS_OP_N : out std_logic_vector(9 downto 0); DAS_trigger_P : out std_logic; DAS_trigger_N : out std_logic; DAS_clk_P : out std_logic; DAS_clk_N : out std_logic; DAS_pvalid_P : out std_logic; DAS_pvalid_N : out std_logic; --Fibre section --- MGT_112 interface -- mgtck3_n : in STD_LOGIC; -- mgtck3_p : in STD_LOGIC; MGTTXP0_112 : out std_logic; MGTTXN0_112 : out std_logic; MGTRXP0_112 : in std_logic; MGTRXN0_112 : in std_logic; MGTRXN1_112 : in std_logic; MGTRXP1_112 : in std_logic; MGTTXN1_112 : out std_logic; MGTTXP1_112 : out std_logic; MGTREFCLKP_112 : in std_logic; MGTREFCLKN_112 : in std_logic; -- --- MGT_114 interface -- MGTTXP0_114 : out std_logic; -- MGTTXN0_114 : out std_logic; -- MGTRXP0_114 : in std_logic; -- MGTRXN0_114 : in std_logic; -- -- MGTRXN1_114 : in std_logic; -- MGTRXP1_114 : in std_logic; -- MGTTXN1_114 : out std_logic; -- MGTTXP1_114 : out std_logic; -- -- MGTREFCLKP_114 : in std_logic; -- MGTREFCLKN_114 : in std_logic; --- MGT_116 interface MGTTXP0_116 : out std_logic; MGTTXN0_116 : out std_logic; MGTRXP0_116 : in std_logic; MGTRXN0_116 : in std_logic; MGTRXN1_116 : in std_logic; MGTRXP1_116 : in std_logic; MGTTXN1_116 : out std_logic; MGTTXP1_116 : out std_logic; MGTREFCLKP_116 : in std_logic; MGTREFCLKN_116 : in std_logic; --monitoring bkpln lv63_P: out std_logic; lv63_N: out std_logic; lv65_P: out std_logic; lv65_N: out std_logic -- ----------------------------------------------------------------- ); end X14_AgFo_V6cp3_SX; ----------------------------------------------------------------- architecture Behavioral of X14_AgFo_V6cp3_SX is ------------ SIGNAL DECLARATION -------------- signal deser_valid_data1,deser_valid_data2,deser_valid_data3,deser_valid_data4, deser_valid_data5,deser_valid_data6,deser_valid_data7,deser_valid_data8, deser_valid_data9,deser_valid_data10,deser_valid_data11,deser_valid_data12, deser_valid_data13,deser_valid_data14,deser_valid_data15,deser_valid_data16 : std_logic := '0'; SIGNAL dina_sig1,dina_sig2,dina_sig3,dina_sig4 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL dina_sig5,dina_sig6,dina_sig7,dina_sig8 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL dina_sig9,dina_sig10,dina_sig11,dina_sig12 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL dina_sig13,dina_sig14,dina_sig15,dina_sig16 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL doutb_sig1,doutb_sig2,doutb_sig3,doutb_sig4 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL doutb_sig5,doutb_sig6,doutb_sig7,doutb_sig8 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL doutb_sig9,doutb_sig10,doutb_sig11,doutb_sig12 : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL doutb_sig13,doutb_sig14,doutb_sig15,doutb_sig16 : STD_LOGIC_VECTOR(9 DOWNTO 0); signal burst_rd_complete, burst_rd_complete1, burst_rd_complete2, burst_rd_complete3, burst_rd_complete4, burst_rd_complete5, burst_rd_complete6, burst_rd_complete7, burst_rd_complete8, burst_rd_complete9, burst_rd_complete10, burst_rd_complete11, burst_rd_complete12, burst_rd_complete13, burst_rd_complete14, burst_rd_complete15, burst_rd_complete16 : std_logic; signal deser_command, delay_ce, delay_inc_dec : std_logic_vector(15 downto 0) := X"0000"; signal usb_command : std_logic_vector(31 downto 0) := X"00000000"; SIGNAL rden_sig1,rden_sig2,rden_sig3,rden_sig4 : std_logic := '0'; signal rden_sig5,rden_sig6,rden_sig7,rden_sig8 : std_logic := '0'; signal rden_sig9,rden_sig10,rden_sig11,rden_sig12: std_logic := '0'; signal rden_sig13,rden_sig14,rden_sig15,rden_sig16 : STD_LOGIC; ----------------------------------------------------------------- SIGNAL din : STD_LOGIC_VECTOR(159 DOWNTO 0); SIGNAL led_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal vsib_pvalid, vsib_trigger : std_logic := '0'; signal burst_mode,ch_sel_mode,fifo_rd_er_flag : std_logic := '0'; signal DATA_READY_OUT_1A_P1,DATA_READY_OUT_1A_P2,DATA_READY_OUT_1B_P1,DATA_READY_OUT_1B_P2, DATA_READY_OUT_1C_P1,DATA_READY_OUT_1C_P2,DATA_READY_OUT_1D_P1,DATA_READY_OUT_1D_P2, DATA_READY_OUT_2A_P1,DATA_READY_OUT_2A_P2,DATA_READY_OUT_2B_P1,DATA_READY_OUT_2B_P2, DATA_READY_OUT_2C_P1,DATA_READY_OUT_2C_P2,DATA_READY_OUT_2D_P1,DATA_READY_OUT_2D_P2 : std_logic :='0'; signal vsib_data: std_logic_VECTOR(9 downto 0); signal SCTN,SCTN_L1,RST,SCTN_DELAYED : STD_LOGIC; signal clk_in,fifo_rd_clk,regceb : std_logic := '0'; signal fds1_1A_clk1buf, fdb2_1B_clk1buf,fds3_1C_clk1buf : std_logic; signal fds6_2B_clk1buf,fda7_2C_clk1buf : std_logic; signal fck4_1D_clk2bufg : std_logic; signal fck5_2A_clk2bufg, fck8_2D_clk2bufg : std_logic; signal data_ready_1A_p1,data_ready_1A_p2,data_ready_1B_p1,data_ready_1B_p2, data_ready_1C_p1,data_ready_1C_p2,data_ready_1D_p1,data_ready_1D_p2, data_ready_2A_p1,data_ready_2A_p2,data_ready_2B_p1,data_ready_2B_p2, data_ready_2C_p1,data_ready_2C_p2,data_ready_2D_p1,data_ready_2D_p2 :std_logic:='0'; signal usb_load,usb_load_delay,usb_reset,usb_reset_chno :std_logic:= '0'; signal sctn_clk, fout_clk, sctn_clk1 : std_logic := '0'; signal chip_sel : std_logic_vector(1 downto 0) := "00"; signal read_reg : std_logic_vector(31 downto 0); signal read_start, read_started,fifo_rdclk, burst_rd_synch : std_logic := '0'; signal fds1_1A_clk1bufr,fdb2_1B_clk1bufr,fds3_1C_clk1bufr,fds6_2B_clk1bufr, fda7_2C_clk1bufr, fck3_1C_clk2bufg : std_logic := '0'; --signal ram_dina_out1 ,ram_dina_out2,ram_dina_out3,ram_dina_out4, SIGNAL ram_dina_out1 ,ram_dina_out2,ram_dina_out3,ram_dina_out4,ram_dina_out5,ram_dina_out6,ram_dina_out7, ram_dina_out8,ram_dina_out9,ram_dina_out10,ram_dina_out11,ram_dina_out12, ram_dina_out13,ram_dina_out14,ram_dina_out15,ram_dina_out16 : std_logic_vector(9 downto 0); --signal ram_addra_out1,ram_addra_out2,ram_addra_out3,ram_addra_out4, signal ram_addra_out1,ram_addra_out2,ram_addra_out3,ram_addra_out4,ram_addra_out5,ram_addra_out6,ram_addra_out7, ram_addra_out8,ram_addra_out9,ram_addra_out10,ram_addra_out11,ram_addra_out12, ram_addra_out13,ram_addra_out14,ram_addra_out15,ram_addra_out16 : std_logic_vector(9 downto 0); --signal ram_wea_out1 , ram_wea_out2,ram_wea_out3,ram_wea_out4, signal ram_wea_out1 ,ram_wea_out2,ram_wea_out3,ram_wea_out4,ram_wea_out5,ram_wea_out6,ram_wea_out7,ram_wea_out8, ram_wea_out9,ram_wea_out10,ram_wea_out11,ram_wea_out12,ram_wea_out13,ram_wea_out14, ram_wea_out15,ram_wea_out16 : std_logic_vector( 0 downto 0); --signal ram_clkb_out1, ram_clkb_out2,ram_clkb_out3,ram_clkb_out4, signal ram_clkb_out1, ram_clkb_out2,ram_clkb_out3,ram_clkb_out4,ram_clkb_out5,ram_clkb_out6,ram_clkb_out7,ram_clkb_out8, ram_clkb_out9,ram_clkb_out10,ram_clkb_out11,ram_clkb_out12,ram_clkb_out13,ram_clkb_out14, ram_clkb_out15,ram_clkb_out16 : std_logic; --ram_addrb_out1, ram_addrb_out2,ram_addrb_out3,ram_addrb_out4, signal ram_addrb_out1, ram_addrb_out2,ram_addrb_out3,ram_addrb_out4,ram_addrb_out5,ram_addrb_out6,ram_addrb_out7,ram_addrb_out8, ram_addrb_out9,ram_addrb_out10,ram_addrb_out11,ram_addrb_out12,ram_addrb_out13,ram_addrb_out14, ram_addrb_out15,ram_addrb_out16 : std_logic_vector(9 downto 0); ---------- When using the Timing simulation uncomment this one. signal dinL1_out : std_logic_vector(159 downto 0); signal regcebL1_out,chsel_opreg_load : std_logic; signal A1_clk, B1_clk, C1_clk, D1_clk, A2_clk, B2_clk, C2_clk, D2_clk : std_logic; signal ADFB_DAT_A1, ADFB_DAT_B1, ADFB_DAT_C1, ADFB_DAT_D1 : std_logic_vector(4 downto 0); signal ADFB_DAT_A2, ADFB_DAT_B2, ADFB_DAT_C2, ADFB_DAT_D2 : std_logic_vector(4 downto 0); signal data_ready_mux_A1, data_ready_mux_B1, data_ready_mux_C1, data_ready_mux_D1: std_logic; signal data_ready_mux_A2, data_ready_mux_B2, data_ready_mux_C2, data_ready_mux_D2: std_logic; signal Ndata_ready_mux_C1,clk200,RDY,RDY1,RDY2,RDY3,RDY4,RDY5,RDY6,RDY7,LRST1: std_logic; signal delay_ce_out1 : std_logic_vector(8 downto 0); signal channel_selected: std_logic_vector(4 downto 0); signal channel_no: std_logic_vector(7 downto 0); signal usbL1 : std_logic_vector(31 downto 0); signal check_ld_low,usb_load_int,valid_load : std_logic; signal ch_sel_reg,ch_sel_reg1,ch_sel_reg_fiber : std_logic_vector(7 downto 0); signal ch_sel_reg_fiber_VSIB : std_logic_vector(7 downto 0); ----------------------------------------------------------------- ------------------- COMPONENTs DECLARATION ---------------------- ----------- DCM for the fifo_rd_clk component fifo_clk_gen1 Port ( clk_in : in std_logic; reset_in : in std_logic; clk_out : out std_logic; clk200 : out std_logic; lock_out : out std_logic ); end component; --component fifo_clk_gen2 -- Port ( -- clk_in : in std_logic; -- reset_in : in std_logic; -- lock_out1: out std_logic; -- lock_out2: out std_logic; -- clk30 : out std_logic; -- clk163 : out std_logic -- ); --end component; ----------- Backplane input module declaration component agfo_bkpl_inputs Port ( clk_in : in std_logic; clk200 : in std_logic; delay_ce : in std_logic; delay_inc_dec : in std_logic; RESET_IN : in std_logic; LRST1 : in std_logic; deser_command_in : in std_logic; data_ready_mux_A1: in std_logic; data_in : in std_logic_vector(4 downto 0); load_pulse : out std_logic; data_ready_A1 : out std_logic; A1_Ldata_P1 : out std_logic_vector(9 downto 0); A1_Ldata_P2 : out std_logic_vector(9 downto 0) ); end component; component agfo_bkpl_inputs_C1_P1P2 Port ( clk_in : in std_logic; clk200 : in std_logic; delay_ce : in std_logic; delay_inc_dec : in std_logic; RESET_IN : in std_logic; LRST1 : in std_logic; deser_command_in : in std_logic; data_ready_mux_A1: in std_logic; data_in : in std_logic_vector(4 downto 0); load_pulse : out std_logic; data_ready_C1 : out std_logic; A1_Ldata_P1 : out std_logic_vector(9 downto 0); A1_Ldata_P2 : out std_logic_vector(9 downto 0) ); end component; ------- RAM DECLARATION component ip_dpram1 Port ( reset_in : in std_logic; clk_in : in std_logic; sctn_in : in std_logic; fout_in : in std_logic; burst_rd_synch_in : in std_logic; burst_mode_in : in std_logic; ch_sel_mode_in : in std_logic; ser_data_ready_in : in std_logic; valid_data_5clk_in : in std_logic; read_start_in : in std_logic; read_started_in : in std_logic; data_in : in std_logic_VECTOR(9 downto 0); -- usb_data_in : in STD_LOGIC_VECTOR (31 downto 0); -- usb_load_in : in STD_LOGIC; -- channel_no : out STD_LOGIC_VECTOR (7 downto 0); ch_sel_reg : in STD_LOGIC_VECTOR (7 downto 0); ch_sel_reg1 : in STD_LOGIC_VECTOR (7 downto 0); ram_dina_out : out std_logic_vector(9 downto 0); ram_addra_out : out std_logic_VECTOR(9 downto 0); ram_wea_out : out std_logic_VECTOR(0 downto 0); ram_clkb_out : out std_logic; ram_addrb_out : out std_logic_VECTOR(9 downto 0); valid_data : out std_logic; regceb_out : out std_logic; data_out : out std_logic_VECTOR(9 downto 0); burst_rd_complete_out : out std_logic ); end component; --------- Output FIFO Declaration component op_fifo1 Port ( reset : in std_logic; USB_RST : in std_logic; rd_clk_in : in std_logic; wr_clk_in : in std_logic; sctn_in : in std_logic; fout_in : in std_logic; -- rd_addr_inc_out : out std_logic; burst_mode_in : in std_logic; ch_sel_mode_in : in std_logic; data_in : in std_logic_VECTOR(159 downto 0); regceb : in std_logic; burst_rd_complete_in : in std_logic; valid_data : in std_logic; channel_no : in STD_LOGIC_VECTOR (7 downto 0); ch_sel_reg : in std_logic_vector(7 downto 0); dinL1_out : out std_logic_Vector(159 downto 0); regcebL1_out : out std_logic; fifo_rd_er_flag_out : out std_logic; vsib_pvalid_out : out std_logic; vsib_trigger_out : out std_logic; read_start_out : out std_logic; read_started_out : out std_logic; mux1_out : out std_logic_vector(9 downto 0); regceb_flag_MON : out std_logic ); end component; signal DATA_TO_VSIB : std_logic_vector(159 downto 0); signal REGCEB_TO_VSIB : std_logic; signal FIBRE_BKPLN_SEL : std_logic; signal VSIB_FIBRE_NUM : std_logic_vector(1 downto 0); signal no_of_chns_TO_VSIB,ch_sel_reg_out: std_logic_vector( 7 downto 0); ---------- XST black box declaration --attribute box_type : string; --attribute box_type of ram1024 : component is "black_box"; ------------ XST black box declaration --attribute box_type : string; --attribute box_type of fifo1 : component is "black_box"; component AGFO_SYNC Port ( clk_in : in STD_LOGIC; -- clk_in1 : in STD_LOGIC; sctn_in : in std_logic; sctn_clk_in_out : out std_logic; fout_clk_in_out : out std_logic; burst_rd_synch_out : out std_logic ); end component; component op_module1 Port ( data_in : in std_logic_vector(9 downto 0); rd_clk_in : in std_logic; reset_in : in std_logic; vsib_pvalid_in : in std_logic; vsib_trigger_in : in std_logic; DAS_OP_P : out std_logic_vector(9 downto 0); DAS_OP_N : out std_logic_vector(9 downto 0); DAS_trigger_P : out std_logic; DAS_trigger_N : out std_logic; DAS_clk_P : out std_logic; DAS_clk_N : out std_logic; DAS_pvalid_P : out std_logic; DAS_pvalid_N : out std_logic ); end component; --component op_module2a -- Port ( -- data_in : in std_logic_vector(9 downto 0); -- rd_clk_in : in std_logic; -- reset_in : in std_logic; -- vsib_pvalid_in : in std_logic; -- vsib_trigger_in : in std_logic; -- -- lv1_n : out STD_LOGIC; -- lv1_p : out STD_LOGIC; -- lv2_n : out STD_LOGIC; -- lv2_p : out STD_LOGIC; -- lv3_n : out STD_LOGIC; -- lv3_p : out STD_LOGIC; -- lv4_n : out STD_LOGIC; -- lv4_p : out STD_LOGIC; -- lv5_n : out STD_LOGIC; -- lv5_p : out STD_LOGIC; -- lv6_n : out STD_LOGIC; -- lv6_p : out STD_LOGIC; -- lv7_n : out STD_LOGIC; -- lv7_p : out STD_LOGIC; -- lv8_n : out STD_LOGIC; -- lv8_p : out STD_LOGIC; -- lv9_n : out STD_LOGIC; -- lv9_p : out STD_LOGIC; -- lv10_n : out STD_LOGIC; -- lv10_p : out STD_LOGIC; -- lv11_n : out STD_LOGIC; -- lv11_p : out STD_LOGIC; -- lv12_n : out STD_LOGIC; -- lv12_p : out STD_LOGIC; -- lv65_n : out STD_LOGIC; -- lv65_p : out STD_LOGIC -- -- ); --end component; component usb_agfo5 Port ( CLK : in std_logic; CLK2 : in std_logic; SCTN : in std_logic; RESET_IN : IN STD_LOGIC; U_WR_usb : IN STD_LOGIC; U_RD_usb : IN STD_LOGIC; U_ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CHIP_SEL : IN STD_LOGIC_VECTOR(1 downto 0); U_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); READ_REG : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); tile0_refclkout_i_out : IN STD_LOGIC; tile1_refclkout_i_out : IN STD_LOGIC; TILE0_TXUSRCLK20_OUT : IN STD_LOGIC; TILE1_TXUSRCLK20_OUT : IN STD_LOGIC; tile0_rxclk0_i : IN STD_LOGIC; tile0_rxclk1_i : IN STD_LOGIC; tile1_rxclk0_i : IN STD_LOGIC; tile1_rxclk1_i : IN STD_LOGIC; mgtreset : IN STD_LOGIC; POL_SELECTION : OUT STD_LOGIC; PIPELINE_EN : OUT STD_LOGIC; OUTPUT_REG : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); WALSH_WREN_out : OUT STD_LOGIC; WALSH_OPREG_LOAD : OUT STD_LOGIC; FIBER_OPREG_LOAD : OUT STD_LOGIC; GAIN_WREN1_out : OUT STD_LOGIC; GAIN_WREN2_out : OUT STD_LOGIC; CHSEL_WREN_out : OUT STD_LOGIC; OPREG_LOAD_out : OUT STD_LOGIC; SER_WREN_out : OUT STD_LOGIC; SER_OPREG_LOAD : OUT STD_LOGIC; SCTN_WREN_out : OUT STD_LOGIC; SCTN_OPREG_LOAD : OUT STD_LOGIC; EXTRST_WR_EN : OUT STD_LOGIC; RST_OPREG_LOAD : OUT STD_LOGIC; OPREG_RDEN : OUT STD_LOGIC ); end component; signal fiber_opreg_load : std_logic; signal DELAY_ENABLE, DELAY_LOAD_PULSE: std_logic; signal TO_USB_READ1 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TO_USB_READ2 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TO_USB_READ3 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TO_USB_READ4 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TO_USB_READ5 : STD_LOGIC_VECTOR(31 DOWNTO 0); component usb_command1 Port ( reset_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load_in : in std_logic; clk_in : in std_logic; deser_command_out : out std_logic_vector(15 downto 0); burst_mode_out : out std_logic; ch_sel_mode_out : out std_logic ); end component; ------------------------------------------------------------- component usb_ipram_chsel Port ( reset_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load_in : in std_logic; clk_in : in std_logic; ch_sel_reg : out std_logic_vector(7 downto 0); ch_sel_reg1 : out std_logic_vector(7 downto 0) ); end component; ------------------------------------------------------------- --component delay_command -- Port ( -- reset_in : in std_logic; -- usb_data_in : in std_logic_vector(31 downto 0); -- usb_load_in : in std_logic; -- clk_in : in std_logic; ---- delay_ce_out : out std_logic_vector(15 downto 0); ---- delay_inc_dec : out std_logic_vector(15 downto 0) -- -- delay_ce_out : out std_logic_vector(15 downto 0); -- delay_ce_out1 : out std_logic_vector(8 downto 0); -- delay_inc_dec : out std_logic_vector(15 downto 0) -- -- ); --end component; component SIM_RESET_MGT_MODEL port ( GSR_IN : in std_logic ); end component; component ml402_sctn_distcard_163MHz Port ( CLK163 : in std_logic; tsctn1_fdce : out std_logic; tsctn2_fdce : out std_logic ); end component; -- sysmon interface signals signal den_cnt : std_logic_vector(15 downto 0); signal BUSY,DRDY,EOS,DEN : std_logic; signal ALM : std_logic_vector(2 downto 0); signal CHANNEL : std_logic_vector(4 downto 0); signal DADDR : std_logic_vector(6 downto 0); signal DO : std_logic_vector(15 downto 0); -- mgt_signal interface signal tile0_plllkdet_i,tile1_plllkdet_i,tile0_clkdet_i,tile1_clkdet_i : std_logic; signal tile0_rxclk0_i,tile0_rxclk1_i,tile1_rxclk0_i,tile1_rxclk1_i : std_logic; signal system_reset : std_logic; signal rxn_in_i,rxp_in_i,txn_out_i,txp_out_i : std_logic_vector(3 downto 0); signal tile0_rxdata0_i : std_logic_vector(15 downto 0); signal tile0_rxdata1_i : std_logic_vector(15 downto 0); signal tile1_rxdata0_i : std_logic_vector(15 downto 0); signal tile1_rxdata1_i : std_logic_vector(15 downto 0); signal mgtreset,WRCLK : std_logic; signal CLK_125 ,USB_CLK,WRCLK_sig,WRCLK1_sig,RDCLK,RDCLK_sig: std_logic; signal tile0_txcharisk0_i ,tile0_txcharisk1_i : std_logic_vector(1 downto 0); signal tile1_txcharisk0_i ,tile1_txcharisk1_i : std_logic_vector(1 downto 0); signal tile0_rxcharisk0_i ,tile0_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile1_rxcharisk0_i ,tile1_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile0_txdata0_i : std_logic_vector(15 downto 0); signal tile0_txdata1_i : std_logic_vector(15 downto 0); signal tile1_txdata0_i : std_logic_vector(15 downto 0); signal tile1_txdata1_i : std_logic_vector(15 downto 0); component EXAMPLE_MGT_TOP generic ( EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 0; EXAMPLE_LANE_WITH_START_CHAR : integer := 0; EXAMPLE_WORDS_IN_BRAM : integer := 512; EXAMPLE_SIM_GTPRESET_SPEEDUP : integer := 1; EXAMPLE_SIM_PLL_PERDIV2 : bit_vector:= x"190"; EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets ); port ( TILE0_REFCLK_PAD_N_IN : in std_logic; TILE0_REFCLK_PAD_P_IN : in std_logic; TILE1_REFCLK_PAD_N_IN : in std_logic; TILE1_REFCLK_PAD_P_IN : in std_logic; GTPRESET_IN : in std_logic; TILE0_PLLLKDET_OUT : out std_logic; TILE1_PLLLKDET_OUT : out std_logic; TILE0_CLKDET_OUT : out std_logic; TILE1_CLKDET_OUT : out std_logic; GTP_SYSTEM_RESET : out std_logic; TILE0_RXCLK0_OUT : out std_logic; TILE0_RXCLK1_OUT : out std_logic; TILE1_RXCLK0_OUT : out std_logic; TILE1_RXCLK1_OUT : out std_logic; TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA1_OUT : out std_logic_vector(15 downto 0); RXN_IN : in std_logic_vector(3 downto 0); RXP_IN : in std_logic_vector(3 downto 0); TXN_OUT : out std_logic_vector(3 downto 0); TXP_OUT : out std_logic_vector(3 downto 0); tile0_txcharisk0_i : in std_logic_vector(1 downto 0); tile0_txcharisk1_i : in std_logic_vector(1 downto 0); tile1_txcharisk0_i : in std_logic_vector(1 downto 0); tile1_txcharisk1_i : in std_logic_vector(1 downto 0); tile0_txdata0_i : in std_logic_vector(15 downto 0); tile0_txdata1_i : in std_logic_vector(15 downto 0); tile1_txdata0_i : in std_logic_vector(15 downto 0); tile1_txdata1_i : in std_logic_vector(15 downto 0); txchardispmode1 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval1 : in std_logic_vector (1 downto 0); -- to MGT; txchardispmode2 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval2 : in std_logic_vector (1 downto 0); -- to MGT; txchardispmode3 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval3 : in std_logic_vector (1 downto 0); -- to MGT; txchardispmode4 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval4 : in std_logic_vector (1 downto 0); -- to MGT; TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); tile0_refclk_out : out std_logic; tile1_refclk_out : out std_logic; TILE0TX_RST : out std_logic; TILE1TX_RST : out std_logic; TILE0RX_RST0 : out std_logic; TILE0RX_RST1 : out std_logic; TILE1RX_RST0 : out std_logic; TILE1RX_RST1 : out std_logic; TILE0_TXUSRCLK20_OUT : out std_logic; TILE1_TXUSRCLK20_OUT : out std_logic; refclkout_pll2_locked_out : out std_logic; refclkout_pll5_locked_out : out std_logic; rxrecclk_dcm0_locked_out : out std_logic; rxrecclk_dcm3_locked_out : out std_logic; rxrecclk_dcm1_locked_out : out std_logic; rxrecclk_dcm4_locked_out : out std_logic; RXRESET0_IN1 : in std_logic; RXRESET0_IN2 : in std_logic; RXRESET0_IN3 : in std_logic; RXRESET0_IN4 : in std_logic; TXKERR0_1 : out std_logic_vector(1 downto 0); TXKERR1_2 : out std_logic_vector(1 downto 0); TXKERR0_3 : out std_logic_vector(1 downto 0); TXKERR1_4 : out std_logic_vector(1 downto 0); TXRUNDISP0_1 : out std_logic_vector(1 downto 0); TXRUNDISP1_2 : out std_logic_vector(1 downto 0); TXRUNDISP0_3 : out std_logic_vector(1 downto 0); TXRUNDISP1_4 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_1 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_2 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_3 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_4 : out std_logic_vector(1 downto 0); RXSTATUS0_1 : out std_logic_vector(2 downto 0); RXSTATUS1_2 : out std_logic_vector(2 downto 0); RXSTATUS0_3 : out std_logic_vector(2 downto 0); RXSTATUS1_4 : out std_logic_vector(2 downto 0); PHYSTATUS0_1 : out std_logic; PHYSTATUS1_2 : out std_logic; PHYSTATUS0_3 : out std_logic; PHYSTATUS1_4 : out std_logic; rxelecidle0_1 : out std_logic; rxelecidle1_2 : out std_logic; rxelecidle0_3 : out std_logic; rxelecidle1_4 : out std_logic; RXPRBSERR0_1 : out std_logic; RXPRBSERR1_2 : out std_logic; RXPRBSERR0_3 : out std_logic; RXPRBSERR1_4 : out std_logic; RXRUNDISP0_1 : out std_logic_vector(1 downto 0); RXRUNDISP1_2 : out std_logic_vector(1 downto 0); RXRUNDISP0_3 : out std_logic_vector(1 downto 0); RXRUNDISP1_4 : out std_logic_vector(1 downto 0); tile0_resetdone0_i_out : out std_logic; tile0_resetdone1_i_out : out std_logic; tile1_resetdone0_i_out : out std_logic; tile1_resetdone1_i_out : out std_logic; tile0_refclkout_i_out : out std_logic; tile1_refclkout_i_out : out std_logic; tile0_rxlossofsync0_i_out : out std_logic_vector(1 downto 0); tile0_rxlossofsync1_i_out : out std_logic_vector(1 downto 0); tile1_rxlossofsync0_i_out : out std_logic_vector(1 downto 0); tile1_rxlossofsync1_i_out : out std_logic_vector(1 downto 0); tile0_rxchanrealign0_i_out : out std_logic; tile0_rxchanrealign1_i_out : out std_logic; tile1_rxchanrealign0_i_out : out std_logic; tile1_rxchanrealign1_i_out : out std_logic; tile0_rxchanisaligned0_i_out : out std_logic; tile0_rxchanisaligned1_i_out : out std_logic; tile1_rxchanisaligned0_i_out : out std_logic; tile1_rxchanisaligned1_i_out : out std_logic; tile0_rxbufstatus0_i_out : out std_logic_vector(2 downto 0); tile0_rxbufstatus1_i_out : out std_logic_vector(2 downto 0); tile1_rxbufstatus0_i_out : out std_logic_vector(2 downto 0); tile1_rxbufstatus1_i_out : out std_logic_vector(2 downto 0); tile0_rxcommadet0_i_out : out std_logic; tile0_rxcommadet1_i_out : out std_logic; tile1_rxcommadet0_i_out : out std_logic; tile1_rxcommadet1_i_out : out std_logic; tile0_rxbyterealign0_i_out : out std_logic; tile0_rxbyterealign1_i_out : out std_logic; tile1_rxbyterealign0_i_out : out std_logic; tile1_rxbyterealign1_i_out : out std_logic; tile0_rxbyteisaligned0_i_out : out std_logic; tile0_rxbyteisaligned1_i_out : out std_logic; tile1_rxbyteisaligned0_i_out : out std_logic; tile1_rxbyteisaligned1_i_out : out std_logic; tile0_rxnotintable0_i_out : out std_logic_vector(1 downto 0); tile0_rxnotintable1_i_out : out std_logic_vector(1 downto 0); tile1_rxnotintable0_i_out : out std_logic_vector(1 downto 0); tile1_rxnotintable1_i_out : out std_logic_vector(1 downto 0); tile0_rxdisperr0_i_out : out std_logic_vector(1 downto 0); tile0_rxdisperr1_i_out : out std_logic_vector(1 downto 0); tile1_rxdisperr0_i_out : out std_logic_vector(1 downto 0); tile1_rxdisperr1_i_out : out std_logic_vector(1 downto 0); tile0_rxchariscomma0_i_out : out std_logic_vector(1 downto 0); tile0_rxchariscomma1_i_out : out std_logic_vector(1 downto 0); tile1_rxchariscomma0_i_out : out std_logic_vector(1 downto 0); tile1_rxchariscomma1_i_out : out std_logic_vector(1 downto 0) ); end component; signal tile0_refclk_out,tile1_refclk_out : std_logic; signal TILE0_TXUSRCLK20_OUT,TILE0TX_RST : std_logic; signal TILE1_TXUSRCLK20_OUT,TILE1TX_RST : std_logic; signal TILE0RX_RST0,TILE0RX_RST1 : std_logic; signal TILE1RX_RST0,TILE1RX_RST1 : std_logic; signal tile1_chardispmode0 : std_logic_vector (1 downto 0); -- to MGT; signal tile1_txchardispval0 : std_logic_vector (1 downto 0); -- to MGT; signal tile0_chardispmode0 : std_logic_vector (1 downto 0); -- to MGT; signal tile0_txchardispval0 : std_logic_vector (1 downto 0); -- to MGT; signal tile0_chardispmode1 : std_logic_vector (1 downto 0); -- to MGT; signal tile0_txchardispval1 : std_logic_vector (1 downto 0); -- to MGT; signal tile1_chardispmode1 : std_logic_vector (1 downto 0); -- to MGT; signal tile1_txchardispval1 : std_logic_vector (1 downto 0); -- to MGT; signal TXKERR0_1 : std_logic_vector(1 downto 0); signal TXKERR1_2 : std_logic_vector(1 downto 0); signal TXKERR0_3 : std_logic_vector(1 downto 0); signal TXKERR1_4 : std_logic_vector(1 downto 0); signal TXRUNDISP0_1 : std_logic_vector(1 downto 0); signal TXRUNDISP1_2 : std_logic_vector(1 downto 0); signal TXRUNDISP0_3 : std_logic_vector(1 downto 0); signal TXRUNDISP1_4 : std_logic_vector(1 downto 0); signal TXBUFSTATUS0_1 : std_logic_vector(1 downto 0); signal TXBUFSTATUS1_2 : std_logic_vector(1 downto 0); signal TXBUFSTATUS0_3 : std_logic_vector(1 downto 0); signal TXBUFSTATUS1_4 : std_logic_vector(1 downto 0); signal RXSTATUS0_1 : std_logic_vector(2 downto 0); signal RXSTATUS1_2 : std_logic_vector(2 downto 0); signal RXSTATUS0_3 : std_logic_vector(2 downto 0); signal RXSTATUS1_4 : std_logic_vector(2 downto 0); signal PHYSTATUS0_1 : std_logic; signal PHYSTATUS1_2 : std_logic; signal PHYSTATUS0_3 : std_logic; signal PHYSTATUS1_4 : std_logic; signal rxelecidle0_1 : std_logic; signal rxelecidle1_2 : std_logic; signal rxelecidle0_3 : std_logic; signal rxelecidle1_4 : std_logic; signal RXPRBSERR0_1 : std_logic; signal RXPRBSERR1_2 : std_logic; signal RXPRBSERR0_3 : std_logic; signal RXPRBSERR1_4 : std_logic; signal RXRUNDISP0_1 : std_logic_vector(1 downto 0); signal RXRUNDISP1_2 : std_logic_vector(1 downto 0); signal RXRUNDISP0_3 : std_logic_vector(1 downto 0); signal RXRUNDISP1_4 : std_logic_vector(1 downto 0); signal tile0_resetdone0_i_out : std_logic; signal tile0_resetdone1_i_out : std_logic; signal tile1_resetdone0_i_out : std_logic; signal tile1_resetdone1_i_out : std_logic; signal tile0_refclkout_i_out : std_logic; signal tile1_refclkout_i_out : std_logic; signal tile0_rxlossofsync0_i_out : std_logic_vector(1 downto 0); signal tile0_rxlossofsync1_i_out : std_logic_vector(1 downto 0); signal tile1_rxlossofsync0_i_out : std_logic_vector(1 downto 0); signal tile1_rxlossofsync1_i_out : std_logic_vector(1 downto 0); signal tile0_rxchanrealign0_i_out : std_logic; signal tile0_rxchanrealign1_i_out : std_logic; signal tile1_rxchanrealign0_i_out : std_logic; signal tile1_rxchanrealign1_i_out : std_logic; signal tile0_rxchanisaligned0_i_out : std_logic; signal tile0_rxchanisaligned1_i_out : std_logic; signal tile1_rxchanisaligned0_i_out : std_logic; signal tile1_rxchanisaligned1_i_out : std_logic; signal tile0_rxbufstatus0_i_out : std_logic_vector(2 downto 0); signal tile0_rxbufstatus1_i_out : std_logic_vector(2 downto 0); signal tile1_rxbufstatus0_i_out : std_logic_vector(2 downto 0); signal tile1_rxbufstatus1_i_out : std_logic_vector(2 downto 0); signal tile0_rxcommadet0_i_out : std_logic; signal tile0_rxcommadet1_i_out : std_logic; signal tile1_rxcommadet0_i_out : std_logic; signal tile1_rxcommadet1_i_out : std_logic; signal tile0_rxbyterealign0_i_out : std_logic; signal tile0_rxbyterealign1_i_out : std_logic; signal tile1_rxbyterealign0_i_out : std_logic; signal tile1_rxbyterealign1_i_out : std_logic; signal tile0_rxbyteisaligned0_i_out : std_logic; signal tile0_rxbyteisaligned1_i_out : std_logic; signal tile1_rxbyteisaligned0_i_out : std_logic; signal tile1_rxbyteisaligned1_i_out : std_logic; signal tile0_rxnotintable0_i_out : std_logic_vector(1 downto 0); signal tile0_rxnotintable1_i_out : std_logic_vector(1 downto 0); signal tile1_rxnotintable0_i_out : std_logic_vector(1 downto 0); signal tile1_rxnotintable1_i_out : std_logic_vector(1 downto 0); signal tile0_rxdisperr0_i_out : std_logic_vector(1 downto 0); signal tile0_rxdisperr1_i_out : std_logic_vector(1 downto 0); signal tile1_rxdisperr0_i_out : std_logic_vector(1 downto 0); signal tile1_rxdisperr1_i_out : std_logic_vector(1 downto 0); signal tile0_rxchariscomma0_i_out : std_logic_vector(1 downto 0); signal tile0_rxchariscomma1_i_out : std_logic_vector(1 downto 0); signal tile1_rxchariscomma0_i_out : std_logic_vector(1 downto 0); signal tile1_rxchariscomma1_i_out : std_logic_vector(1 downto 0); COMPONENT trans_test2b Port ( clk_165 : in STD_LOGIC; -- clk_125 : in STD_LOGIC; rst : in STD_LOGIC; sctn_in : in STD_LOGIC; valid_regceb : in STD_LOGIC; valid_enable : in STD_LOGIC; valid_data : in STD_LOGIC_VECTOR (159 downto 0); fout : in STD_LOGIC; TILE0_TXUSRCLK20 : in STD_LOGIC; TILE1_TXUSRCLK20 : in STD_LOGIC; TILE0TX_RST : in STD_LOGIC; TILE1TX_RST : in STD_LOGIC; fibre_no : in STD_LOGIC_VECTOR(2 downto 0); no_ch_fibre1 : in STD_LOGIC_VECTOR(2 downto 0); --0 to 7 chs no_ch_fibre2 : in STD_LOGIC_VECTOR(2 downto 0); --8 to 15 chs no_ch_fibre3 : in STD_LOGIC_VECTOR(2 downto 0); --16 to 23 chs no_ch_fibre4 : in STD_LOGIC_VECTOR(2 downto 0); --24 to 31 chs actual_diag : in STD_LOGIC; node_in : in STD_LOGIC_VECTOR(7 downto 0); ---Outputs dout1 : out STD_LOGIC_VECTOR (15 downto 0); dout2 : out STD_LOGIC_VECTOR (15 downto 0); dout3 : out STD_LOGIC_VECTOR (15 downto 0); dout4 : out STD_LOGIC_VECTOR (15 downto 0); charisk1 : out STD_LOGIC_VECTOR (1 downto 0); charisk2 : out STD_LOGIC_VECTOR (1 downto 0); charisk3 : out STD_LOGIC_VECTOR (1 downto 0); charisk4 : out STD_LOGIC_VECTOR (1 downto 0); txchardispmode1 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval1 : out std_logic_vector (1 downto 0); -- to MGT; txchardispmode2 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval2 : out std_logic_vector (1 downto 0); -- to MGT; txchardispmode3 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval3 : out std_logic_vector (1 downto 0); -- to MGT; txchardispmode4 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval4 : out std_logic_vector (1 downto 0); -- to MGT; ip_dpram_en : out STD_LOGIC; data_load_MON : out STD_LOGIC; valid_enableL1_MON: out STD_LOGIC ); end COMPONENT; signal fibre_no : STD_LOGIC_VECTOR(2 downto 0); signal no_ch_fibre1 : STD_LOGIC_VECTOR(2 downto 0); --0 to 7 chs signal no_ch_fibre2 : STD_LOGIC_VECTOR(2 downto 0); --8 to 15 chs signal no_ch_fibre3 : STD_LOGIC_VECTOR(2 downto 0); --16 to 23 chs signal no_ch_fibre4 : STD_LOGIC_VECTOR(2 downto 0); --24 to 31 chs signal actual_diag : STD_LOGIC; signal node : STD_LOGIC_VECTOR(7 downto 0); signal TX_RESET : STD_LOGIC; component agfo_mgt_receiver Port ( rst : in STD_LOGIC; RX_RST : in STD_LOGIC; clk_125 : in STD_LOGIC; clk_165 : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (15 downto 0); charisk : in STD_LOGIC_VECTOR (1 downto 0); chselreg : in STD_LOGIC_VECTOR (2 downto 0); regceb_out : out STD_LOGIC; valid_data : out STD_LOGIC; data_out : out STD_LOGIC_VECTOR (159 downto 0); node_seq_reg : out STD_LOGIC_VECTOR (31 downto 0); RxSeq : out STD_LOGIC_VECTOR (21 downto 0) ); end component; signal regceb_out_F1 : STD_LOGIC; signal data_out_F1 : STD_LOGIC_VECTOR (159 downto 0); signal node_seq_reg_F1 : STD_LOGIC_VECTOR (31 downto 0); signal VALID_EN_F1 : STD_LOGIC; signal regceb_out_F2 : STD_LOGIC; signal data_out_F2 : STD_LOGIC_VECTOR (159 downto 0); signal node_seq_reg_F2 : STD_LOGIC_VECTOR (31 downto 0); signal VALID_EN_F2 : STD_LOGIC; signal regceb_out_F3 : STD_LOGIC; signal data_out_F3 : STD_LOGIC_VECTOR (159 downto 0); signal node_seq_reg_F3 : STD_LOGIC_VECTOR (31 downto 0); signal VALID_EN_F3 : STD_LOGIC; signal regceb_out_F4 : STD_LOGIC; signal data_out_F4 : STD_LOGIC_VECTOR (159 downto 0); signal node_seq_reg_F4 : STD_LOGIC_VECTOR (31 downto 0); signal VALID_EN_F4 : STD_LOGIC; signal valid_en1,valid_en2,valid_en3,valid_en4 : std_logic; signal valid_en5,valid_en6,valid_en7,valid_en8 : std_logic; signal valid_en9,valid_en10,valid_en11,valid_en12 : std_logic; signal valid_en13,valid_en14,valid_en15,valid_en16 : std_logic; signal valid_enable : std_logic; signal VALID_EN_TO_VSIB : std_logic; component rst_module1_usb Port ( clk_in : in STD_LOGIC; -- ext_rst_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load : in std_logic; refclkout_pll2_locked_out: in std_logic; refclkout_pll5_locked_out: in std_logic; rxrecclk_dcm0_locked_out : in std_logic; rxrecclk_dcm3_locked_out : in std_logic; rxrecclk_dcm1_locked_out : in std_logic; rxrecclk_dcm4_locked_out : in std_logic; -- counter_out : out std_logic_vector(15 downto 0); ms6a_out : out std_logic; reset_out : out std_logic; MGT_RESET : out std_logic; GLOBAL_RESET : out std_logic; rx1_RESET : out std_logic; rx2_RESET : out std_logic; rx3_RESET : out std_logic; rx4_RESET : out std_logic ); end component; signal RXRESET0_IN1,RXRESET0_IN2,RXRESET0_IN3,RXRESET0_IN4 : std_logic; signal RXRESET0_IN1_L1,check_ld_low1,rx_slide1 : std_logic; signal RXRESET0_IN1_L2,check_ld_low2,rx_slide2 : std_logic; signal RXRESET0_IN1_L3,check_ld_low3,rx_slide3 : std_logic; signal RXRESET0_IN1_L4,check_ld_low4,rx_slide4 : std_logic; component usb_command_fiber Port ( RST_USB : in std_logic; clk_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load1 : in std_logic; usb_load2 : in std_logic; FIBRE_BKPLN_SEL : out std_logic; ch_sel_reg_out : out std_logic_vector(7 downto 0); VSIB_FIBRE_NUM : out std_logic_vector(1 downto 0); fibre_no_out : out STD_LOGIC_VECTOR(2 downto 0); no_ch_fibre1_out : out STD_LOGIC_VECTOR(2 downto 0); --0 to 7 chs no_ch_fibre2_out : out STD_LOGIC_VECTOR(2 downto 0); --8 to 15 chs no_ch_fibre3_out : out STD_LOGIC_VECTOR(2 downto 0); --16 to 23 chs no_ch_fibre4_out : out STD_LOGIC_VECTOR(2 downto 0); --24 to 31 chs actual_diag : out std_logic; node : out STD_LOGIC_VECTOR(7 downto 0) ); end component; component delay_load_PULSE_GEN Port ( reset_in : in std_logic; clk_in : in std_logic; DELAY_ENABLE : in std_logic; DELAY_LOAD_PULSE : in std_logic; usb_command : in std_logic_vector(31 downto 0); LOAD_PULSE1 : out std_logic; LOAD_PULSE2 : out std_logic; LOAD_PULSE3 : out std_logic; LOAD_PULSE4 : out std_logic; LOAD_PULSE5 : out std_logic; LOAD_PULSE6 : out std_logic; LOAD_PULSE7 : out std_logic; LOAD_PULSE8 : out std_logic; LOAD_PULSE9 : out std_logic; usb_command_L1 : out std_logic_vector(31 downto 0) ); end component; -------------------------- component delay_control_module Port ( reset_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load_in : in std_logic; clk_in : in std_logic; -- CLK200 -- input_sig : in std_logic; -- lrst : out std_logic; delay_inc_dec1 : out std_logic; delay_inc_dec2 : out std_logic; delay_inc_dec3 : out std_logic; delay_inc_dec4 : out std_logic; delay_ce1 : out std_logic; delay_ce2 : out std_logic; delay_ce3 : out std_logic; delay_ce4 : out std_logic; stop1_mon : out std_logic; i1_mon : out std_logic; usb_load_int_mon : out std_logic; lreset_mon : out std_logic ); end component; signal DELAY_LOAD_PULSE1,DELAY_LOAD_PULSE2,DELAY_LOAD_PULSE3,DELAY_LOAD_PULSE4 : std_logic; signal DELAY_LOAD_PULSE5,DELAY_LOAD_PULSE6,DELAY_LOAD_PULSE7,DELAY_LOAD_PULSE8 : std_logic; signal DELAY_LOAD_PULSE9: std_logic; ------------- signal usb_command_L1 : std_logic_vector(31 downto 0); signal delay_inc_dec_data_A1, delay_inc_dec_mux_A1, delay_inc_dec_clk_A1 : std_logic; signal delay_ce_data_A1, delay_ce_mux_A1, delay_ce_clk_A1 : std_logic; signal delay_inc_dec_data_A2, delay_inc_dec_mux_A2, delay_inc_dec_clk_A2 : std_logic; signal delay_ce_data_A2, delay_ce_mux_A2, delay_ce_clk_A2 : std_logic; signal delay_inc_dec_data_A3, delay_inc_dec_mux_A3, delay_inc_dec_clk_A3 : std_logic; signal delay_ce_data_A3, delay_ce_mux_A3, delay_ce_clk_A3 : std_logic; signal delay_inc_dec_data_A4, delay_inc_dec_mux_A4, delay_inc_dec_clk_A4 : std_logic; signal delay_ce_data_A4, delay_ce_mux_A4, delay_ce_clk_A4 : std_logic; signal delay_inc_dec_data_A5, delay_inc_dec_mux_A5, delay_inc_dec_clk_A5 : std_logic; signal delay_ce_data_A5, delay_ce_mux_A5, delay_ce_clk_A5 : std_logic; signal delay_inc_dec_data_A6, delay_inc_dec_mux_A6, delay_inc_dec_clk_A6 : std_logic; signal delay_ce_data_A6, delay_ce_mux_A6, delay_ce_clk_A6 : std_logic; signal delay_inc_dec_data_A7, delay_inc_dec_mux_A7, delay_inc_dec_clk_A7 : std_logic; signal delay_ce_data_A7, delay_ce_mux_A7, delay_ce_clk_A7 : std_logic; signal delay_inc_dec_data_A8, delay_inc_dec_mux_A8, delay_inc_dec_clk_A8 : std_logic; signal delay_ce_data_A8, delay_ce_mux_A8, delay_ce_clk_A8 : std_logic; signal delay_inc_dec_sctn,delay_ce_sctn : std_logic; signal GLOBAL_RESET,USB_RST : std_logic; signal refclkout_pll2_locked_out: std_logic; signal refclkout_pll5_locked_out,refclkout_pll5_locked_out1: std_logic; signal rxrecclk_dcm0_locked_out : std_logic; signal rxrecclk_dcm3_locked_out : std_logic; signal rxrecclk_dcm1_locked_out : std_logic; signal rxrecclk_dcm4_locked_out : std_logic; signal CLK125_MGT,lock_out,lock_out1,lock_out2,clk125mhz,open_clk,SCTN_1 : std_logic; signal data_load_MON, valid_enableL1_MON, regceb_flag_MON,clkip: std_logic; signal SCTN_buf,SCTN_DELAYED1,RX_SYNC,RX_SYNCL1 : std_logic; signal RxSeq_F1,RxSeq_F2,RxSeq_F3,RxSeq_F4 : STD_LOGIC_VECTOR (21 downto 0); ----------- End of Components Definitions ----------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- begin ----------------------------------------------------------------- --------- Test points for the Timing Simulation ----------------- --dina_sig1_out <= dina_sig1; --deser_valid_data1_out <= deser_valid_data1; --DATA_READY_OUT_1A_P1_out <= DATA_READY_OUT_1A_P1; --dina_sig2_out <= dina_sig2; --deser_valid_data2_out <= deser_valid_data2; --DATA_READY_OUT_1A_P2_out <= DATA_READY_OUT_1A_P2; --dina_sig3_out <= dina_sig3; --deser_valid_data3_out <= deser_valid_data3; --DATA_READY_OUT_1B_P1_out <= DATA_READY_OUT_1B_P1; --dina_sig4_out <= dina_sig4; --deser_valid_data4_out <= deser_valid_data4; --DATA_READY_OUT_1B_P2_out <= DATA_READY_OUT_1B_P2; ----------------------------------------------------------------- IDELAYCTRL_inst0 : IDELAYCTRL port map ( RDY => RDY, -- 1-bit output indicates validity of the REFCLK REFCLK => clk200, -- 1-bit reference clock input RST => LRST1 -- 1-bit reset input ); IDELAYCTRL_inst1 : IDELAYCTRL port map ( RDY => RDY1, -- 1-bit output indicates validity of the REFCLK REFCLK => clk200, -- 1-bit reference clock input RST => LRST1 -- 1-bit reset input ); IDELAYCTRL_inst2 : IDELAYCTRL port map ( RDY => RDY2, -- 1-bit output indicates validity of the REFCLK REFCLK => clk200, -- 1-bit reference clock input RST => LRST1 -- 1-bit reset input ); IDELAYCTRL_inst3 : IDELAYCTRL port map ( RDY => RDY3, -- 1-bit output indicates validity of the REFCLK REFCLK => clk200, -- 1-bit reference clock input RST => LRST1 -- 1-bit reset input ); IDELAYCTRL_SCTN_inst : IDELAYCTRL port map ( RDY => RDY4, -- 1-bit output indicates validity of the REFCLK REFCLK => clk200, -- 1-bit reference clock input RST => LRST1 -- 1-bit reset input ); process(clk200) begin if clk200'event and clk200= '1' then LRST1 <= GLOBAL_RESET; --RST; end if; end process; -- ----------------------------------------------------------------- chip_sel <= "00"; ----------------------------------------------------------------- sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL port map ( GSR_IN => mgtreset ); rstm : rst_module1_usb port map( clk_in => clk_in, usb_data_in => usb_command, usb_load => usb_reset_chno, refclkout_pll2_locked_out => '1', --refclkout_pll2_locked_out, refclkout_pll5_locked_out => '1', --refclkout_pll5_locked_out, rxrecclk_dcm0_locked_out => '1', --rxrecclk_dcm0_locked_out, rxrecclk_dcm3_locked_out => '1', --rxrecclk_dcm3_locked_out, rxrecclk_dcm1_locked_out => '1', --rxrecclk_dcm1_locked_out, rxrecclk_dcm4_locked_out => '1', --rxrecclk_dcm4_locked_out, ms6a_out => open, reset_out => USB_RST, MGT_RESET => mgtreset, GLOBAL_RESET=> GLOBAL_RESET, rx1_RESET => RXRESET0_IN1, rx2_RESET => RXRESET0_IN2, rx3_RESET => RXRESET0_IN3, rx4_RESET => RXRESET0_IN4 ); --mgtreset <= '0'; ----------------------------------------------------------------- --------- DCM for the fifo_rd_clk fifo_clock_gen : fifo_clk_gen1 Port map ( clk_in => clk_in, reset_in => GLOBAL_RESET, --RST, clk_out => fifo_rd_clk, clk200 => clk200, lock_out => open ); ----------------------------------------------------------------------------- --section used when independent clkin and sctn were generated inside -- fifo_clock_gen : fifo_clk_gen2 -- Port map ( -- clk_in => CLK125_MGT, -- reset_in => USB_RST, -- lock_out1 => lock_out1, -- lock_out2 => lock_out2, -- clk30 => fifo_rd_clk, -- usb clk and opfifo rd clk -- clk163 => clk_in -- clk163. -- ); -- --clk165_inst : IBUFGDS -- generic map ( -- CAPACITANCE => "DONT_CARE", -- DIFF_TERM => true, -- IBUF_DELAY_VALUE => "0", -- IOSTANDARD => "LVDS_25") -- port map ( -- O => CLK125_MGT,--clklocal, -- Clock buffer output -- I => mgtck3_p, -- Diff_p clock buffer input -- IB => mgtck3_n-- Diff_n clock buffer input -- ); --sctngen: ml402_sctn_distcard_163MHz -- Port map( -- CLK163 => clk_in, -- tsctn1_fdce => SCTN_1, -- tsctn2_fdce => open -- ); -- --FDCPE_sctn_inst : FDCPE -- generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') -- port map ( -- Q => SCTN_L1, -- Data output -- C => clk_in, -- Clock input -- CE => '1', -- Clock enable input -- CLR => '0', -- Asynchronous clear input -- D => SCTN_1, --SCTN, -- Data input -- PRE => '0' -- Asynchronous set input -- ); -- --------------------------------------------------------------------------- chip_sel <= "00"; ----------------------------------------------------------------- agfo_sctn_sync: AGFO_SYNC Port map ( clk_in => clk_in, -- clk_in1 => fifo_rd_clk, sctn_in => SCTN_L1, sctn_clk_in_out => sctn_clk, fout_clk_in_out => fout_clk, burst_rd_synch_out => burst_rd_synch ); ----------------------------------------------------------------- usb_if_inst1 : usb_agfo5 Port map( CLK => fifo_rd_clk, CLK2 => clk_in, SCTN => SCTN_L1, RESET_IN => USB_RST, --mgtreset, --GLOBAL_RESET, --RST, U_WR_usb => WR, U_RD_usb => RD, U_ADDR => An, CHIP_SEL => chip_sel, U_DATA => Dn, READ_REG => read_reg, TO_USB_READ1 => TO_USB_READ1, TO_USB_READ2 => TO_USB_READ2, TO_USB_READ3 => TO_USB_READ3, TO_USB_READ4 => TO_USB_READ4, TO_USB_READ5 => TO_USB_READ5, tile0_refclkout_i_out => tile0_refclkout_i_out, tile1_refclkout_i_out => tile1_refclkout_i_out, TILE0_TXUSRCLK20_OUT => '0',--TILE0_TXUSRCLK20_OUT, TILE1_TXUSRCLK20_OUT => '0',--TILE1_TXUSRCLK20_OUT, tile0_rxclk0_i => '0',--tile0_rxclk0_i, tile0_rxclk1_i => '0',--tile0_rxclk1_i, tile1_rxclk0_i => '0',--tile1_rxclk0_i, tile1_rxclk1_i => '0',--tile1_rxclk1_i, mgtreset => mgtreset, POL_SELECTION => open, PIPELINE_EN => open, OUTPUT_REG => usb_command, WALSH_WREN_out => open, WALSH_OPREG_LOAD => usb_load, FIBER_OPREG_LOAD => FIBER_OPREG_LOAD, GAIN_WREN1_out => open, GAIN_WREN2_out => open, CHSEL_WREN_out => DELAY_ENABLE, OPREG_LOAD_out => DELAY_LOAD_PULSE, SER_WREN_out => open, SER_OPREG_LOAD => usb_load_delay, SCTN_WREN_out => open, SCTN_OPREG_LOAD => chsel_opreg_load, EXTRST_WR_EN => open, RST_OPREG_LOAD => usb_reset_chno, OPREG_RDEN => open ); ----------------------------------------------------------------- usb_command_inst1 : usb_command1 Port map ( reset_in => USB_RST, --GLOBAL_RESET, --RST, usb_data_in => usb_command, usb_load_in => usb_load, clk_in => clk_in, deser_command_out => deser_command, burst_mode_out => burst_mode, ch_sel_mode_out => ch_sel_mode ); ----------------------------------------------------------------- usb_ipram_chsel_inst1 : usb_ipram_chsel Port map ( reset_in => USB_RST, --GLOBAL_RESET, --RST, usb_data_in => usb_command, usb_load_in => chsel_opreg_load, clk_in => clk_in, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1 ); ----------------------------------------------------------------- --delay_command_inst1 : delay_command -- Port map ( -- reset_in => USB_RST, --GLOBAL_RESET, --RST, -- usb_data_in => usb_command, -- usb_load_in => usb_load_delay, -- clk_in => clk200, ---- delay_ce_out => delay_ce, ---- delay_inc_dec => delay_inc_dec -- -- delay_ce_out => delay_ce, -- delay_ce_out1 => delay_ce_out1, -- delay_inc_dec => delay_inc_dec -- -- -- ); delay_load_inst : delay_load_PULSE_GEN Port map ( reset_in => GLOBAL_RESET, --USB_RST, clk_in => fifo_rd_clk, DELAY_ENABLE => DELAY_ENABLE, DELAY_LOAD_PULSE => DELAY_LOAD_PULSE, usb_command => usb_command, LOAD_PULSE1 => DELAY_LOAD_PULSE1, LOAD_PULSE2 => DELAY_LOAD_PULSE2, LOAD_PULSE3 => DELAY_LOAD_PULSE3, LOAD_PULSE4 => DELAY_LOAD_PULSE4, LOAD_PULSE5 => DELAY_LOAD_PULSE5, LOAD_PULSE6 => DELAY_LOAD_PULSE6, LOAD_PULSE7 => DELAY_LOAD_PULSE7, LOAD_PULSE8 => DELAY_LOAD_PULSE8, LOAD_PULSE9 => DELAY_LOAD_PULSE9, usb_command_L1 => usb_command_L1 ); delaypulse_gen1 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE1, clk_in => clk200, delay_inc_dec1 => open, --delay_inc_dec_data_A1, delay_inc_dec2 => open, --delay_inc_dec_mux_A1, delay_inc_dec3 => open, --delay_inc_dec_clk_A1, delay_inc_dec4 => delay_inc_dec_sctn, delay_ce1 => open, --delay_ce_data_A1, delay_ce2 => open, --delay_ce_mux_A1, delay_ce3 => open, --delay_ce_clk_A1, delay_ce4 => delay_ce_sctn, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen2 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE2, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A1, --delay_inc_dec_data_A2, delay_inc_dec2 => delay_inc_dec_mux_A1, --delay_inc_dec_mux_A2, delay_inc_dec3 => delay_inc_dec_clk_A1, --delay_inc_dec_clk_A2, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A1, --delay_ce_data_A2, delay_ce2 => delay_ce_mux_A1, --delay_ce_data_A2, delay_ce3 => delay_ce_clk_A1, --delay_ce_clk_A2, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen3 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE3, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A2, --delay_inc_dec_data_A3, delay_inc_dec2 => delay_inc_dec_mux_A2, --delay_inc_dec_mux_A3, delay_inc_dec3 => delay_inc_dec_clk_A2, --delay_inc_dec_clk_A3, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A2, --delay_ce_data_A3, delay_ce2 => delay_ce_mux_A2, --delay_ce_mux_A3, delay_ce3 => delay_ce_clk_A2, --delay_ce_clk_A3, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen4 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE4, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A3, --delay_inc_dec_data_A4, delay_inc_dec2 => delay_inc_dec_mux_A3, --delay_inc_dec_mux_A4, delay_inc_dec3 => delay_inc_dec_clk_A3, --delay_inc_dec_clk_A4, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A3, --delay_ce_data_A4, delay_ce2 => delay_ce_mux_A3, --delay_ce_mux_A4, delay_ce3 => delay_ce_clk_A3, --delay_ce_clk_A4, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen5 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE5, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A4, --delay_inc_dec_data_A5, delay_inc_dec2 => delay_inc_dec_mux_A4, --delay_inc_dec_mux_A5, delay_inc_dec3 => delay_inc_dec_clk_A4, --delay_inc_dec_clk_A5, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A4, --delay_ce_data_A5, delay_ce2 => delay_ce_mux_A4, --delay_ce_mux_A5, delay_ce3 => delay_ce_clk_A4, --delay_ce_clk_A5, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen6 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE6, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A5, --delay_inc_dec_data_A6, delay_inc_dec2 => delay_inc_dec_mux_A5, --delay_inc_dec_mux_A6, delay_inc_dec3 => delay_inc_dec_clk_A5, --delay_inc_dec_clk_A6, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A5, --delay_ce_data_A6, delay_ce2 => delay_ce_mux_A5, --delay_ce_mux_A6, delay_ce3 => delay_ce_clk_A5, --delay_ce_clk_A6, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen7 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE7, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A6, --delay_inc_dec_data_A7, delay_inc_dec2 => delay_inc_dec_mux_A6, --delay_inc_dec_mux_A7, delay_inc_dec3 => delay_inc_dec_clk_A6, --delay_inc_dec_clk_A7, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A6, --delay_ce_data_A7, delay_ce2 => delay_ce_mux_A6, --delay_ce_mux_A7, delay_ce3 => delay_ce_clk_A6, --delay_ce_clk_A7, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen8 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE8, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A7, --delay_inc_dec_data_A8, delay_inc_dec2 => delay_inc_dec_mux_A7, --delay_inc_dec_mux_A8, delay_inc_dec3 => delay_inc_dec_clk_A7, --delay_inc_dec_clk_A8, delay_inc_dec4 => open, delay_ce1 => delay_ce_data_A7, --delay_ce_data_A8, delay_ce2 => delay_ce_mux_A7, --delay_ce_mux_A8, delay_ce3 => delay_ce_clk_A7, --delay_ce_clk_A8, delay_ce4 => open, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); delaypulse_gen9 : delay_control_module Port map ( reset_in => GLOBAL_RESET, --USB_RST, usb_data_in => usb_command_L1, usb_load_in => DELAY_LOAD_PULSE9, clk_in => clk200, delay_inc_dec1 => delay_inc_dec_data_A8, --open, delay_inc_dec2 => delay_inc_dec_mux_A8, --open, delay_inc_dec3 => delay_inc_dec_clk_A8, --open, delay_inc_dec4 => open, --delay_inc_dec_sctn, delay_ce1 => delay_ce_data_A8, --open, delay_ce2 => delay_ce_mux_A8, --open, delay_ce3 => delay_ce_clk_A8, --open, delay_ce4 => open, --delay_ce_sctn, stop1_mon => open, i1_mon => open, usb_load_int_mon => open, lreset_mon => open ); ----------------------------------------------------------------- clk165 : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => true, IBUF_DELAY_VALUE => "0", IOSTANDARD => "LVDS_25") port map ( O => clkip, --clk_in, -- Clock buffer output I => lv67_p, -- Diff_p clock buffer input IB => lv67_n -- Diff_n clock buffer input ); clkinbufg : BUFG port map ( O => clk_in, -- Clock buffer output I => clkip --clk_in -- Clock buffer input ); --------------------------------------------------------------- IBUFGDS_sctn_se_inst : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => true, IBUF_DELAY_VALUE => "0", IOSTANDARD => "LVDS_25") port map ( O => SCTN, -- Clock buffer output I => lv69_p, -- Diff_p clock buffer input IB => lv69_n -- Diff_n clock buffer input ); IDELAY_SCTN_inst : IDELAY generic map ( IOBDELAY_TYPE => "VARIABLE", -- "DEFAULT", "FIXED" or "VARIABLE" IOBDELAY_VALUE => 0) -- Any value from 0 to 63 port map ( O => SCTN_DELAYED, -- 1-bit output C => clk200, -- 1-bit clock input CE => delay_ce_sctn, --delay_ce_out1(0), -- 1-bit clock enable input I => SCTN, -- 1-bit data input INC => delay_inc_dec_sctn,--delay_inc_dec(0), -- 1-bit increment input RST => LRST1 -- 1-bit reset input ); --sctnbufg : BUFG -- port map ( -- O => SCTN_DELAYED1, -- Clock buffer output -- I => SCTN_DELAYED --clk_in -- Clock buffer input -- ); -- --FDCPE_sctn_inst : FDCPE -- generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') -- port map ( -- Q => SCTN_DELAYED, -- Data output -- C => clk_in, -- Clock input -- CE => '1', -- Clock enable input -- CLR => '0', -- Asynchronous clear input -- D => SCTN, --SCTN_DELAYED, --SCTN, -- Data input -- PRE => '0' -- Asynchronous set input -- ); FDCPE_sctn_inst1 : FDCPE generic map ( INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => SCTN_L1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- Asynchronous clear input D => SCTN_DELAYED, --SCTN_DELAYED, --SCTN, -- Data input PRE => '0' -- Asynchronous set input ); ---------------------------------------------------------------- ----------------------------------------------------------------- -- Differential Input Buffers for the differential input signals IBUFDS_inst_A1: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_A1(i), -- Clock buffer output I => ADFB_DAT_A1_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_A1_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_A1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>A1_clk, -- Clock buffer output I => ADFB_CLK_A1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_A1_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_A1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_A1, -- Clock buffer output I => DATA_READY_A1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_A1_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- IBUFDS_inst_B1: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_B1(i), -- Clock buffer output I => ADFB_DAT_B1_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_B1_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_B1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>B1_clk, -- Clock buffer output I => ADFB_CLK_B1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_B1_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_B1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_B1, -- Clock buffer output I => DATA_READY_B1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_B1_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- IBUFDS_inst_C1: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_C1(i), -- Clock buffer output I => ADFB_DAT_C1_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_C1_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_C1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>C1_clk, -- Clock buffer output I => ADFB_CLK_C1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_C1_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_C1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_C1, -- Clock buffer output I => DATA_READY_C1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB => DATA_READY_C1_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- IBUFDS_inst_D1: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_D1(i), -- Clock buffer output I => ADFB_DAT_D1_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_D1_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_D1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>D1_clk, -- Clock buffer output I => ADFB_CLK_D1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_D1_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_D1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_D1, -- Clock buffer output I => DATA_READY_D1_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_D1_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- ----------------------------------------------------------------- IBUFDS_inst_A2: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_A2(i), -- Clock buffer output I => ADFB_DAT_A2_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_A2_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_A2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>A2_clk, -- Clock buffer output I => ADFB_CLK_A2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_A2_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_A2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_A2, -- Clock buffer output I => DATA_READY_A2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_A2_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- IBUFDS_inst_B2: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_B2(i), -- Clock buffer output I => ADFB_DAT_B2_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_B2_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_B2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>B2_clk, -- Clock buffer output I => ADFB_CLK_B2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_B2_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_B2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_B2, -- Clock buffer output I => DATA_READY_B2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_B2_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- IBUFDS_inst_C2: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_C2(i), -- Clock buffer output I => ADFB_DAT_C2_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_C2_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_C2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>C2_clk, -- Clock buffer output I => ADFB_CLK_C2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_C2_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_C2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_C2, -- Clock buffer output I => DATA_READY_C2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_C2_N -- Diff_n clock buffer input (connect directly to top-level port) ); ----------------------------------------------------------------- IBUFDS_inst_D2: FOR i IN 0 to 4 GENERATE BEGIN IBUFDS_inst_i : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>ADFB_DAT_D2(i), -- Clock buffer output I => ADFB_DAT_D2_P(i), -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_DAT_D2_N(i) -- Diff_n clock buffer input (connect directly to top-level port) ); END GENERATE; IBUFDS_inst_CLK_D2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>D2_clk, -- Clock buffer output I => ADFB_CLK_D2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>ADFB_CLK_D2_N -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFDS_inst_DR_D2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "LVDS_25") port map ( O =>data_ready_mux_D2, -- Clock buffer output I => DATA_READY_D2_P, -- Diff_p clock buffer input (connect directly to top-level port) IB =>DATA_READY_D2_N -- Diff_n clock buffer input (connect directly to top-level port) ); ---------------------------- ----------------------------------------------- ----------------------------------------------------------------- ---- Backplane Input Module ------------------------------------- ----------------------------------------------------------------- agfo_bkpl_inputs_inst_A1_P1P2 : agfo_bkpl_inputs Port map( clk_in => A1_clk, clk200 => clk200, delay_ce => delay_ce_clk_A1, --delay_ce(8), delay_inc_dec => delay_inc_dec_clk_A1,--delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(0), data_ready_mux_A1=> data_ready_mux_A1, data_in => ADFB_DAT_A1, load_pulse => deser_valid_data1, data_ready_A1 => DATA_READY_OUT_1A_P1, A1_Ldata_P1 => dina_sig1, A1_Ldata_P2 => dina_sig2 ); DATA_READY_OUT_1A_P2 <= DATA_READY_OUT_1A_P1; deser_valid_data2 <= deser_valid_data1; ------------------------------------------------------------------- agfo_bkpl_inputs_inst_B1_P1P2 : agfo_bkpl_inputs Port map( clk_in => B1_clk, clk200 => clk200, delay_ce => delay_ce_clk_A2, --delay_ce(9), delay_inc_dec => delay_inc_dec_clk_A2, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(1), data_ready_mux_A1=> data_ready_mux_B1, data_in => ADFB_DAT_B1, load_pulse => deser_valid_data3, data_ready_A1 => DATA_READY_OUT_1B_P1, A1_Ldata_P1 => dina_sig3, A1_Ldata_P2 => dina_sig4 ); DATA_READY_OUT_1B_P2 <= DATA_READY_OUT_1B_P1; deser_valid_data4 <= deser_valid_data3; --------------------------------------------------------------- agfo_bkpl_inputs_inst_C1_P1P2 : agfo_bkpl_inputs_C1_P1P2 Port map( clk_in => C1_clk, clk200 => clk200, delay_ce => delay_ce_clk_A3, --delay_ce(10), delay_inc_dec => delay_inc_dec_clk_A3, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(2), load_pulse => deser_valid_data5, data_ready_mux_A1=> data_ready_mux_C1, data_ready_C1 => DATA_READY_OUT_1C_P1, data_in => ADFB_DAT_C1, A1_Ldata_P1 => dina_sig5, A1_Ldata_P2 => dina_sig6 ); DATA_READY_OUT_1C_P2 <= DATA_READY_OUT_1C_P1; deser_valid_data6 <= deser_valid_data5; ----------------------------------------------------------------- agfo_bkpl_inputs_inst_D1_P1P2 : agfo_bkpl_inputs Port map( clk_in => D1_clk, clk200 => clk200, delay_ce => delay_ce_clk_A4, --delay_ce(11), delay_inc_dec => delay_inc_dec_clk_A4, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(3), data_ready_mux_A1=> data_ready_mux_D1, data_in => ADFB_DAT_D1, load_pulse => deser_valid_data7, data_ready_A1 => DATA_READY_OUT_1D_P1, A1_Ldata_P1 => dina_sig7, A1_Ldata_P2 => dina_sig8 ); DATA_READY_OUT_1D_P2 <= DATA_READY_OUT_1D_P1; deser_valid_data8 <= deser_valid_data7; ----------------------------------------------------------------- agfo_bkpl_inputs_inst_A2_P1P2 : agfo_bkpl_inputs Port map( clk_in => A2_clk, clk200 => clk200, delay_ce => delay_ce_clk_A5, --delay_ce(12), delay_inc_dec => delay_inc_dec_clk_A5, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(4), data_ready_mux_A1=> data_ready_mux_A2, data_in => ADFB_DAT_A2, load_pulse => deser_valid_data9, data_ready_A1 => DATA_READY_OUT_2A_P1, A1_Ldata_P1 => dina_sig9, A1_Ldata_P2 => dina_sig10 ); DATA_READY_OUT_2A_P2 <= DATA_READY_OUT_2A_P1; deser_valid_data10 <= deser_valid_data9; ----------------------------------------------------------------- agfo_bkpl_inputs_inst_B2_P1P2 : agfo_bkpl_inputs Port map( clk_in => B2_clk, clk200 => clk200, delay_ce => delay_ce_clk_A6, --delay_ce(13), delay_inc_dec => delay_inc_dec_clk_A6, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(5), data_ready_mux_A1=> data_ready_mux_B2, data_in => ADFB_DAT_B2, load_pulse => deser_valid_data11, data_ready_A1 => DATA_READY_OUT_2B_P1, A1_Ldata_P1 => dina_sig11, A1_Ldata_P2 => dina_sig12 ); DATA_READY_OUT_2B_P2 <= DATA_READY_OUT_2B_P1; deser_valid_data12 <= deser_valid_data11; ----------------------------------------------------------------- agfo_bkpl_inputs_inst_C2_P1P2 : agfo_bkpl_inputs Port map( clk_in => C2_clk, clk200 => clk200, delay_ce => delay_ce_clk_A7, --delay_ce(14), delay_inc_dec => delay_inc_dec_clk_A7, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(6), data_ready_mux_A1=> data_ready_mux_C2, data_in => ADFB_DAT_C2, load_pulse => deser_valid_data13, data_ready_A1 => DATA_READY_OUT_2C_P1, A1_Ldata_P1 => dina_sig13, A1_Ldata_P2 => dina_sig14 ); DATA_READY_OUT_2C_P2 <= DATA_READY_OUT_2C_P1; deser_valid_data14 <= deser_valid_data13; ----------------------------------------------------------------- agfo_bkpl_inputs_inst_D2_P1P2 : agfo_bkpl_inputs Port map( clk_in => D2_clk, clk200 => clk200, delay_ce => delay_ce_clk_A8, --delay_ce(15), delay_inc_dec => delay_inc_dec_clk_A8, --delay_inc_dec(0), RESET_IN => GLOBAL_RESET, --RST, LRST1 => LRST1, deser_command_in => deser_command(0), data_ready_mux_A1=> data_ready_mux_D2, data_in => ADFB_DAT_D2, load_pulse => deser_valid_data15, data_ready_A1 => DATA_READY_OUT_2D_P1, A1_Ldata_P1 => dina_sig15, A1_Ldata_P2 => dina_sig16 ); DATA_READY_OUT_2D_P2 <= DATA_READY_OUT_2D_P1; deser_valid_data16 <= deser_valid_data15; ----------------------------------------------------------------- ------------------- End of Backplane input module ------------------------ ------------------ LED's Display (disco!!!)---------------------- process(clk_in) begin IF GLOBAL_RESET = '1' then --RST = '1' then led_cnt <= X"00000000"; elsif clk_in'event and clk_in='1' then led_cnt <= led_cnt + 1; else led_cnt <= led_cnt; end if; end process; led1 <= led_cnt(31); led2 <= led_cnt(30); led3 <= led_cnt(29); led4 <= led_cnt(28); led5 <= led_cnt(27); led6 <= led_cnt(26); led7 <= led_cnt(25); --refclkout_pll5_locked_out; --led_cnt(25); led8 <= led_cnt(24); --refclkout_pll2_locked_out;--; led9 <= RDY3; --led_cnt(23); led10 <= RDY2; ---led_cnt(22); led11 <= RDY1; --led_cnt(21); led12 <= RDY; --led_cnt(20); ----------------------------------------------------------------- ----------------------------------------------------------------- ---- usb load decode for ipram - no of channels -- -------------------------------------------------------------------- --process(clk_in) --begin -- if clk_in'event and clk_in = '1' then -- if(GLOBAL_RESET, --RST = '1') then -- check_ld_low <= '0'; -- end if; -- usb_load_int <= chsel_opreg_load; --usb_load_in; -- if usb_load_int = '1' and check_ld_low = '0' then -- valid_load <= '1'; -- check_ld_low <= '1'; -- elsif usb_load_int = '1' and check_ld_low = '1' then -- valid_load <= valid_load ; -- check_ld_low <= check_ld_low; -- elsif usb_load_int = '0' and check_ld_low = '1' then -- check_ld_low<= '0'; -- valid_load <= valid_load; -- elsif usb_load_int = '0' and check_ld_low = '0' then -- valid_load <= valid_load ; -- check_ld_low<= '0';--check_ld_low; -- end if; -- if valid_load = '1' then -- valid_load <= '0'; -- usbL1 <= usb_command; --usb_data_in; -- end if; -- ch_sel_reg <= usbL1(31 downto 24); -- ch_sel_reg1 <= ch_sel_reg + '1'; -- channel_no <= usbL1(31 downto 24); -- -- end if; --end process; ----------------------------------------------------------------- ----------------------------------------------------------------- ip_dpram_inst1 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1A_P1, valid_data_5clk_in => deser_valid_data1, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig1, ram_dina_out => ram_dina_out1, ram_addra_out => ram_addra_out1, ram_wea_out => ram_wea_out1, ram_clkb_out => ram_clkb_out1, ram_addrb_out => ram_addrb_out1, valid_data => valid_en1, regceb_out => rden_sig1, data_out => doutb_sig1, burst_rd_complete_out => burst_rd_complete1 ); ----------------------------------------------------------------- ip_dpram_inst2 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1A_P2, valid_data_5clk_in => deser_valid_data2, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig2, ram_dina_out => ram_dina_out2, ram_addra_out => ram_addra_out2, ram_wea_out => ram_wea_out2, ram_clkb_out => ram_clkb_out2, ram_addrb_out => ram_addrb_out2, valid_data => valid_en2, regceb_out => rden_sig2, data_out => doutb_sig2, burst_rd_complete_out => burst_rd_complete2 ); ----------------------------------------------------------------- ip_dpram_inst3 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1B_P1, valid_data_5clk_in => deser_valid_data3, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig3, ram_dina_out => ram_dina_out3, ram_addra_out => ram_addra_out3, ram_wea_out => ram_wea_out3, ram_clkb_out => ram_clkb_out3, ram_addrb_out => ram_addrb_out3, valid_data => valid_en3, regceb_out => rden_sig3, data_out => doutb_sig3, burst_rd_complete_out => burst_rd_complete3 ); ----------------------------------------------------------------- ip_dpram_inst4 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk , burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1B_P2, valid_data_5clk_in => deser_valid_data4, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig4, ram_dina_out => ram_dina_out4, ram_addra_out => ram_addra_out4, ram_wea_out => ram_wea_out4, ram_clkb_out => ram_clkb_out4, ram_addrb_out => ram_addrb_out4, valid_data => valid_en4, regceb_out => rden_sig4, data_out => doutb_sig4, burst_rd_complete_out => burst_rd_complete4 ); ----------------------------------------------------------------- ip_dpram_inst5 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1C_P1, valid_data_5clk_in => deser_valid_data5, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig5, ram_dina_out => ram_dina_out5, ram_addra_out => ram_addra_out5, ram_wea_out => ram_wea_out5, ram_clkb_out => ram_clkb_out5, ram_addrb_out => ram_addrb_out5, valid_data => valid_en5, regceb_out => rden_sig5, data_out => doutb_sig5, burst_rd_complete_out => burst_rd_complete5 ); ----------------------------------------------------------------- ip_dpram_inst6 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1C_P2, valid_data_5clk_in => deser_valid_data6, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig6, ram_dina_out => ram_dina_out6, ram_addra_out => ram_addra_out6, ram_wea_out => ram_wea_out6, ram_clkb_out => ram_clkb_out6, ram_addrb_out => ram_addrb_out6, valid_data => valid_en6, regceb_out => rden_sig6, data_out => doutb_sig6, burst_rd_complete_out => burst_rd_complete6 ); ----------------------------------------------------------------- ip_dpram_inst7 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1D_P1, valid_data_5clk_in => deser_valid_data7, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig7, ram_dina_out => ram_dina_out7, ram_addra_out => ram_addra_out7, ram_wea_out => ram_wea_out7, ram_clkb_out => ram_clkb_out7, ram_addrb_out => ram_addrb_out7, valid_data => valid_en7, regceb_out => rden_sig7, data_out => doutb_sig7, burst_rd_complete_out => burst_rd_complete7 ); ----------------------------------------------------------------- ip_dpram_inst8 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_1D_P2, valid_data_5clk_in => deser_valid_data8, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig8, ram_dina_out => ram_dina_out8, ram_addra_out => ram_addra_out8, ram_wea_out => ram_wea_out8, ram_clkb_out => ram_clkb_out8, ram_addrb_out => ram_addrb_out8, valid_data => valid_en8, regceb_out => rden_sig8, data_out => doutb_sig8, burst_rd_complete_out => burst_rd_complete8 ); ----------------------------------------------------------------- ip_dpram_inst9 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk , burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2A_P1, valid_data_5clk_in => deser_valid_data9, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig9, ram_dina_out => ram_dina_out9, ram_addra_out => ram_addra_out9, ram_wea_out => ram_wea_out9, ram_clkb_out => ram_clkb_out9, ram_addrb_out => ram_addrb_out9, valid_data => valid_en9, regceb_out => rden_sig9, data_out => doutb_sig9, burst_rd_complete_out => burst_rd_complete9 ); ----------------------------------------------------------------- ip_dpram_inst10 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2A_P2, valid_data_5clk_in => deser_valid_data10, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig10, ram_dina_out => ram_dina_out10, ram_addra_out => ram_addra_out10, ram_wea_out => ram_wea_out10, ram_clkb_out => ram_clkb_out10, ram_addrb_out => ram_addrb_out10, valid_data => valid_en10, regceb_out => rden_sig10, data_out => doutb_sig10, burst_rd_complete_out => burst_rd_complete10 ); ----------------------------------------------------------------- ip_dpram_inst11 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2B_P1, valid_data_5clk_in => deser_valid_data11, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig11, ram_dina_out => ram_dina_out11, ram_addra_out => ram_addra_out11, ram_wea_out => ram_wea_out11, ram_clkb_out => ram_clkb_out11, ram_addrb_out => ram_addrb_out11, valid_data => valid_en11, regceb_out => rden_sig11, data_out => doutb_sig11, burst_rd_complete_out => burst_rd_complete11 ); ----------------------------------------------------------------- ip_dpram_inst12 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2B_P2, valid_data_5clk_in => deser_valid_data12, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig12, ram_dina_out => ram_dina_out12, ram_addra_out => ram_addra_out12, ram_wea_out => ram_wea_out12, ram_clkb_out => ram_clkb_out12, ram_addrb_out => ram_addrb_out12, valid_data => valid_en12, regceb_out => rden_sig12, data_out => doutb_sig12, burst_rd_complete_out => burst_rd_complete12 ); ----------------------------------------------------------------- ip_dpram_inst13 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2C_P1, valid_data_5clk_in => deser_valid_data13, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig13, ram_dina_out => ram_dina_out13, ram_addra_out => ram_addra_out13, ram_wea_out => ram_wea_out13, ram_clkb_out => ram_clkb_out13, ram_addrb_out => ram_addrb_out13, valid_data => valid_en13, regceb_out => rden_sig13, data_out => doutb_sig13, burst_rd_complete_out => burst_rd_complete13 ); ----------------------------------------------------------------- ip_dpram_inst14 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2C_P2, valid_data_5clk_in => deser_valid_data14, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig14, ram_dina_out => ram_dina_out14, ram_addra_out => ram_addra_out14, ram_wea_out => ram_wea_out14, ram_clkb_out => ram_clkb_out14, ram_addrb_out => ram_addrb_out14, valid_data => valid_en14, regceb_out => rden_sig14, data_out => doutb_sig14, burst_rd_complete_out => burst_rd_complete14 ); ----------------------------------------------------------------- ip_dpram_inst15 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk , burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2D_P1, valid_data_5clk_in => deser_valid_data15, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig15, ram_dina_out => ram_dina_out15, ram_addra_out => ram_addra_out15, ram_wea_out => ram_wea_out15, ram_clkb_out => ram_clkb_out15, ram_addrb_out => ram_addrb_out15, valid_data => valid_en15, regceb_out => rden_sig15, data_out => doutb_sig15, burst_rd_complete_out => burst_rd_complete15 ); ----------------------------------------------------------------- ip_dpram_inst16 : ip_dpram1 Port map( -- usb_data_in => usb_command, -- usb_load_in => chsel_opreg_load, -- channel_no => channel_no, ch_sel_reg => ch_sel_reg, ch_sel_reg1 => ch_sel_reg1, reset_in => GLOBAL_RESET, --RST, clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, burst_rd_synch_in => burst_rd_synch, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, ser_data_ready_in => DATA_READY_OUT_2D_P2, valid_data_5clk_in => deser_valid_data16, read_start_in => read_start, read_started_in => read_started, data_in => dina_sig16, ram_dina_out => ram_dina_out16, ram_addra_out => ram_addra_out16, ram_wea_out => ram_wea_out16, ram_clkb_out => ram_clkb_out16, ram_addrb_out => ram_addrb_out16, valid_data => valid_en16, regceb_out => rden_sig16, data_out => doutb_sig16, burst_rd_complete_out => burst_rd_complete16 ); ----------------------------------------------------------------- ----------------------------------------------------------------- --- Registering the DPRAM outputs for the Output FIFO ----------- process(clk_in) begin if(clk_in'event and clk_in='1') then din(159 DOWNTO 150) <= doutb_sig1; din(149 DOWNTO 140) <= doutb_sig2; -- din(139 DOWNTO 130) <= doutb_sig3; din(130) <= doutb_sig3(0); din(131) <= doutb_sig3(1); din(132) <= not doutb_sig3(2); din(136 DOWNTO 133) <= doutb_sig3(6 DOWNTO 3); din(137) <= not doutb_sig3(7); din(139 DOWNTO 138) <= doutb_sig3(9 DOWNTO 8); -- din(129 DOWNTO 120) <= doutb_sig4; din(120) <= doutb_sig4(0); din(121) <= doutb_sig4(1); din(122) <= not doutb_sig4(2); din(126 DOWNTO 123) <= doutb_sig4(6 DOWNTO 3); din(127) <= not doutb_sig4(7); din(129 DOWNTO 128) <= doutb_sig4(9 DOWNTO 8); -- din(119 DOWNTO 110) <= doutb_sig5; din(110) <= not doutb_sig5(0); din(111) <= not doutb_sig5(1); din(112) <= doutb_sig5(2); din(113) <= not doutb_sig5(3); din(114) <= doutb_sig5(4); din(115) <= not doutb_sig5(5); din(116) <= not doutb_sig5(6); din(117) <= doutb_sig5(7); din(118) <= not doutb_sig5(8); din(119) <= doutb_sig5(9); -- din(109 DOWNTO 100) <= doutb_sig6; din(100) <= not doutb_sig6(0); din(101) <= not doutb_sig6(1); din(102) <= doutb_sig6(2); din(103) <= not doutb_sig6(3); din(104) <= doutb_sig6(4); din(105) <= not doutb_sig6(5); din(106) <= not doutb_sig6(6); din(107) <= doutb_sig6(7); din(108) <= not doutb_sig6(8); din(109) <= doutb_sig6(9); -- din(99 DOWNTO 90) <= doutb_sig7; din(90) <= not doutb_sig7(0); din(91) <= doutb_sig7(1); din(92) <= not doutb_sig7(2); din(93) <= doutb_sig7(3); din(94) <= not doutb_sig7(4); din(95) <= not doutb_sig7(5); din(96) <= doutb_sig7(6); din(97) <= not doutb_sig7(7); din(98) <= doutb_sig7(8); din(99) <= not doutb_sig7(9); -- din(89 DOWNTO 80) <= doutb_sig8; din(80) <= not doutb_sig8(0); din(81) <= doutb_sig8(1); din(82) <= not doutb_sig8(2); din(83) <= doutb_sig8(3); din(84) <= not doutb_sig8(4); din(85) <= not doutb_sig8(5); din(86) <= doutb_sig8(6); din(87) <= not doutb_sig8(7); din(88) <= doutb_sig8(8); din(89) <= not doutb_sig8(9); din(79 DOWNTO 70) <= doutb_sig9; din(69 DOWNTO 60) <= doutb_sig10; din(59 DOWNTO 50) <= doutb_sig11; din(49 DOWNTO 40) <= doutb_sig12; din(39 DOWNTO 30) <= doutb_sig13; din(29 DOWNTO 20) <= doutb_sig14; din(19 DOWNTO 10) <= doutb_sig15; din(9 DOWNTO 0) <= doutb_sig16; regceb <= rden_sig1 or rden_sig2 or rden_sig3 or rden_sig4 or rden_sig5 or rden_sig6 or rden_sig7 or rden_sig8 or rden_sig9 or rden_sig10 or rden_sig11 or rden_sig12 or rden_sig13 or rden_sig14 or rden_sig15 or rden_sig16; burst_rd_complete <= burst_rd_complete1 and burst_rd_complete2 and burst_rd_complete3 and burst_rd_complete4 and burst_rd_complete5 and burst_rd_complete6 and burst_rd_complete7 and burst_rd_complete8 and burst_rd_complete9 and burst_rd_complete10 and burst_rd_complete11 and burst_rd_complete12 and burst_rd_complete13 and burst_rd_complete14 and burst_rd_complete15 and burst_rd_complete16; valid_enable <= valid_en1 or valid_en2 or valid_en3 or valid_en4 or valid_en5 or valid_en6 or valid_en7 or valid_en8 or valid_en9 or valid_en10 or valid_en11 or valid_en12 or valid_en13 or valid_en14 or valid_en15 or valid_en16; -- regceb <= rden_sig1; end if; end process; --lv65_p <= rden_sig1; --lv65_n <= burst_rd_complete1; ----------------------------------------------------------------- usb_fiber: usb_command_fiber Port map ( RST_USB => USB_RST, clk_in => clk_in, usb_data_in => usb_command, usb_load1 => FIBER_OPREG_LOAD, usb_load2 => chsel_opreg_load, FIBRE_BKPLN_SEL => FIBRE_BKPLN_SEL, ch_sel_reg_out => ch_sel_reg_fiber, VSIB_FIBRE_NUM => VSIB_FIBRE_NUM, fibre_no_out => fibre_no, no_ch_fibre1_out => no_ch_fibre1, no_ch_fibre2_out => no_ch_fibre2, no_ch_fibre3_out => no_ch_fibre3, no_ch_fibre4_out => no_ch_fibre4, actual_diag => actual_diag, node => node ); ------------------------- --PACKETIZATION LOGIC TX_RESET <= TILE0TX_RST or TILE1TX_RST; TRANS_TEST: trans_test2b PORT MAP (clk_165 => clk_in, rst => GLOBAL_RESET, --TX_RESET, --RST, sctn_in => sctn_clk, valid_regceb => regceb, valid_enable => valid_enable, valid_data => din, fout => fout_clk, TILE0_TXUSRCLK20 => TILE0_TXUSRCLK20_OUT, --CLK_125, TILE1_TXUSRCLK20 => TILE1_TXUSRCLK20_OUT, --CLK_125, TILE0TX_RST => GLOBAL_RESET, --TX_RESET, --TILE0TX_RST, TILE1TX_RST => GLOBAL_RESET, --TX_RESET, --TILE1TX_RST, fibre_no => fibre_no, no_ch_fibre1 => no_ch_fibre1, no_ch_fibre2 => no_ch_fibre2, no_ch_fibre3 => no_ch_fibre3, no_ch_fibre4 => no_ch_fibre4, actual_diag => actual_diag, node_in => node, ---Outputs -- dout1 => tile0_txdata0_i, -- dout2 => tile0_txdata1_i, -- dout3 => tile1_txdata0_i, -- dout4 => tile1_txdata1_i, dout1 => tile1_txdata0_i, dout2 => tile0_txdata0_i, dout3 => tile0_txdata1_i, dout4 => tile1_txdata1_i, -- charisk1 => tile0_txcharisk0_i, -- charisk2 => tile0_txcharisk1_i, -- charisk3 => tile1_txcharisk0_i, -- charisk4 => tile1_txcharisk1_i, charisk1 => tile1_txcharisk0_i, charisk2 => tile0_txcharisk0_i, charisk3 => tile0_txcharisk1_i, charisk4 => tile1_txcharisk1_i, -- txchardispmode1 => txchardispmode1, -- txchardispval1 => txchardispval1, -- txchardispmode2 => txchardispmode2, -- txchardispval2 => txchardispval2, -- txchardispmode3 => txchardispmode3, -- txchardispval3 => txchardispval3, -- txchardispmode4 => txchardispmode4, -- txchardispval4 => txchardispval4, txchardispmode1 => tile1_chardispmode0, --txchardispmode3, txchardispval1 => tile1_txchardispval0,--txchardispval3, txchardispmode2 => tile0_chardispmode0, --txchardispmode1, txchardispval2 => tile0_txchardispval0, --txchardispval1, txchardispmode3 => tile0_chardispmode1, --txchardispmode1, txchardispval3 => tile0_txchardispval1, --txchardispval1, txchardispmode4 => tile1_chardispmode1, --txchardispmode2, txchardispval4 => tile1_txchardispval1, --txchardispval2, ip_dpram_en => open, data_load_MON => data_load_MON, valid_enableL1_MON => valid_enableL1_MON ); example_mgt_top_i : EXAMPLE_MGT_TOP generic map ( EXAMPLE_SIM_GTPRESET_SPEEDUP => 1, -- Speedup is turned on for simulation EXAMPLE_SIM_PLL_PERDIV2 => x"190", -- Set to the VCO Unit Interval time EXAMPLE_USE_CHIPSCOPE => 0 --1 - use chipscope to drive resets, --0 - drive resets from top level ports ) port map ( TILE0_REFCLK_PAD_N_IN => MGTREFCLKN_112, TILE0_REFCLK_PAD_P_IN => MGTREFCLKP_112, TILE1_REFCLK_PAD_N_IN => MGTREFCLKN_116, TILE1_REFCLK_PAD_P_IN => MGTREFCLKP_116, GTPRESET_IN => mgtreset, TILE0_PLLLKDET_OUT => tile0_plllkdet_i, TILE1_PLLLKDET_OUT => tile1_plllkdet_i, TILE0_CLKDET_OUT => tile0_clkdet_i, TILE1_CLKDET_OUT => tile1_clkdet_i, GTP_SYSTEM_RESET => system_reset, TILE0_RXCLK0_OUT => tile0_rxclk0_i, TILE0_RXCLK1_OUT => tile0_rxclk1_i, TILE1_RXCLK0_OUT => tile1_rxclk0_i, TILE1_RXCLK1_OUT => tile1_rxclk1_i, TILE0_RXDATA0_OUT => tile0_rxdata0_i, TILE0_RXDATA1_OUT => tile0_rxdata1_i, TILE1_RXDATA0_OUT => tile1_rxdata0_i, TILE1_RXDATA1_OUT => tile1_rxdata1_i, RXN_IN => rxn_in_i, RXP_IN => rxp_in_i, TXN_OUT => txn_out_i, TXP_OUT => txp_out_i, tile0_txcharisk0_i => tile0_txcharisk0_i, tile0_txcharisk1_i => tile0_txcharisk1_i, tile1_txcharisk0_i => tile1_txcharisk0_i, tile1_txcharisk1_i => tile1_txcharisk1_i, tile0_txdata0_i => tile0_txdata0_i, tile0_txdata1_i => tile0_txdata1_i, tile1_txdata0_i => tile1_txdata0_i, tile1_txdata1_i => tile1_txdata1_i, txchardispmode1 => tile0_chardispmode0, --txchardispmode1, txchardispval1 => tile0_txchardispval0, --txchardispval1, txchardispmode2 => tile0_chardispmode1, --txchardispmode2, txchardispval2 => tile0_txchardispval1,--txchardispval2, txchardispmode3 => tile1_chardispmode0, --txchardispmode3, txchardispval3 => tile1_txchardispval0, --txchardispval3, txchardispmode4 => tile1_chardispmode1, --txchardispmode4, txchardispval4 => tile1_txchardispval1, --txchardispval4, TILE0_RXCHARISK0_OUT => tile0_rxcharisk0_i, TILE0_RXCHARISK1_OUT => tile0_rxcharisk1_i, TILE1_RXCHARISK0_OUT => tile1_rxcharisk0_i, TILE1_RXCHARISK1_OUT => tile1_rxcharisk1_i, tile0_refclk_out => tile0_refclk_out, tile1_refclk_out => tile1_refclk_out, TILE0TX_RST => TILE0TX_RST, TILE1TX_RST => TILE1TX_RST, TILE0RX_RST0 => TILE0RX_RST0, TILE0RX_RST1 => TILE0RX_RST1, TILE1RX_RST0 => TILE1RX_RST0, TILE1RX_RST1 => TILE1RX_RST1, TILE0_TXUSRCLK20_OUT => TILE0_TXUSRCLK20_OUT, TILE1_TXUSRCLK20_OUT => TILE1_TXUSRCLK20_OUT , refclkout_pll2_locked_out => refclkout_pll2_locked_out, refclkout_pll5_locked_out => refclkout_pll5_locked_out, rxrecclk_dcm0_locked_out => rxrecclk_dcm0_locked_out, rxrecclk_dcm3_locked_out => rxrecclk_dcm3_locked_out, rxrecclk_dcm1_locked_out => rxrecclk_dcm1_locked_out, rxrecclk_dcm4_locked_out => rxrecclk_dcm4_locked_out, RXRESET0_IN1 => '0', --rx_slide1, --RXRESET0_IN1, --'0', RXRESET0_IN2 => '0', --rx_slide2, --RXRESET0_IN2, --'0', RXRESET0_IN3 => '0', --rx_slide3, --RXRESET0_IN3, --'0', RXRESET0_IN4 => '0', --rx_slide4 --RXRESET0_IN4 --'0' TXKERR0_1 => TXKERR0_1, TXKERR1_2 => TXKERR1_2, TXKERR0_3 => TXKERR0_3, TXKERR1_4 => TXKERR1_4, TXRUNDISP0_1 => TXRUNDISP0_1, TXRUNDISP1_2 => TXRUNDISP1_2, TXRUNDISP0_3 => TXRUNDISP0_3, TXRUNDISP1_4 => TXRUNDISP1_4, TXBUFSTATUS0_1 => TXBUFSTATUS0_1, TXBUFSTATUS1_2 => TXBUFSTATUS1_2, TXBUFSTATUS0_3 => TXBUFSTATUS0_3, TXBUFSTATUS1_4 => TXBUFSTATUS1_4, RXSTATUS0_1 => RXSTATUS0_1, RXSTATUS1_2 => RXSTATUS1_2, RXSTATUS0_3 => RXSTATUS0_3, RXSTATUS1_4 => RXSTATUS1_4, PHYSTATUS0_1 => PHYSTATUS0_1, PHYSTATUS1_2 => PHYSTATUS1_2, PHYSTATUS0_3 => PHYSTATUS0_3, PHYSTATUS1_4 => PHYSTATUS1_4, rxelecidle0_1 => rxelecidle0_1, rxelecidle1_2 => rxelecidle1_2, rxelecidle0_3 => rxelecidle0_3, rxelecidle1_4 => rxelecidle1_4, RXPRBSERR0_1 => RXPRBSERR0_1, RXPRBSERR1_2 => RXPRBSERR1_2, RXPRBSERR0_3 => RXPRBSERR0_3, RXPRBSERR1_4 => RXPRBSERR1_4, RXRUNDISP0_1 => RXRUNDISP0_1, RXRUNDISP1_2 => RXRUNDISP1_2, RXRUNDISP0_3 => RXRUNDISP0_3, RXRUNDISP1_4 => RXRUNDISP1_4, tile0_resetdone0_i_out => tile0_resetdone0_i_out, tile0_resetdone1_i_out => tile0_resetdone1_i_out, tile1_resetdone0_i_out => tile1_resetdone0_i_out, tile1_resetdone1_i_out => tile1_resetdone1_i_out, tile0_refclkout_i_out => tile0_refclkout_i_out, tile1_refclkout_i_out => tile1_refclkout_i_out, tile0_rxlossofsync0_i_out => tile0_rxlossofsync0_i_out, tile0_rxlossofsync1_i_out => tile0_rxlossofsync1_i_out, tile1_rxlossofsync0_i_out => tile1_rxlossofsync0_i_out, tile1_rxlossofsync1_i_out => tile1_rxlossofsync1_i_out, tile0_rxchanrealign0_i_out => tile0_rxchanrealign0_i_out, tile0_rxchanrealign1_i_out => tile0_rxchanrealign1_i_out, tile1_rxchanrealign0_i_out => tile1_rxchanrealign0_i_out, tile1_rxchanrealign1_i_out => tile1_rxchanrealign1_i_out, tile0_rxchanisaligned0_i_out => tile0_rxchanisaligned0_i_out, tile0_rxchanisaligned1_i_out => tile0_rxchanisaligned1_i_out, tile1_rxchanisaligned0_i_out => tile1_rxchanisaligned0_i_out, tile1_rxchanisaligned1_i_out => tile1_rxchanisaligned1_i_out, tile0_rxbufstatus0_i_out => tile0_rxbufstatus0_i_out, tile0_rxbufstatus1_i_out => tile0_rxbufstatus1_i_out, tile1_rxbufstatus0_i_out => tile1_rxbufstatus0_i_out, tile1_rxbufstatus1_i_out => tile1_rxbufstatus1_i_out, tile0_rxcommadet0_i_out => tile0_rxcommadet0_i_out, tile0_rxcommadet1_i_out => tile0_rxcommadet1_i_out, tile1_rxcommadet0_i_out => tile1_rxcommadet0_i_out, tile1_rxcommadet1_i_out => tile1_rxcommadet1_i_out, tile0_rxbyterealign0_i_out => tile0_rxbyterealign0_i_out, tile0_rxbyterealign1_i_out => tile0_rxbyterealign1_i_out, tile1_rxbyterealign0_i_out => tile1_rxbyterealign0_i_out, tile1_rxbyterealign1_i_out => tile1_rxbyterealign1_i_out, tile0_rxbyteisaligned0_i_out => tile0_rxbyteisaligned0_i_out, tile0_rxbyteisaligned1_i_out => tile0_rxbyteisaligned1_i_out, tile1_rxbyteisaligned0_i_out => tile1_rxbyteisaligned0_i_out, tile1_rxbyteisaligned1_i_out => tile1_rxbyteisaligned1_i_out, tile0_rxnotintable0_i_out => tile0_rxnotintable0_i_out, tile0_rxnotintable1_i_out => tile0_rxnotintable1_i_out, tile1_rxnotintable0_i_out => tile1_rxnotintable0_i_out, tile1_rxnotintable1_i_out => tile1_rxnotintable1_i_out, tile0_rxdisperr0_i_out => tile0_rxdisperr0_i_out, tile0_rxdisperr1_i_out => tile0_rxdisperr1_i_out, tile1_rxdisperr0_i_out => tile1_rxdisperr0_i_out, tile1_rxdisperr1_i_out => tile1_rxdisperr1_i_out, tile0_rxchariscomma0_i_out => tile0_rxchariscomma0_i_out, tile0_rxchariscomma1_i_out => tile0_rxchariscomma1_i_out, tile1_rxchariscomma0_i_out => tile1_rxchariscomma0_i_out, tile1_rxchariscomma1_i_out => tile1_rxchariscomma1_i_out ); TO_USB_READ1 <= tile1_rxchariscomma1_i_out & tile1_rxchariscomma0_i_out & tile0_rxchariscomma1_i_out & tile0_rxchariscomma1_i_out & tile1_rxdisperr1_i_out & tile1_rxdisperr0_i_out & tile0_rxdisperr1_i_out & tile0_rxdisperr0_i_out & tile1_rxnotintable1_i_out & tile1_rxnotintable0_i_out & tile0_rxnotintable1_i_out & tile0_rxnotintable0_i_out & tile1_rxlossofsync1_i_out & tile1_rxlossofsync0_i_out & tile0_rxlossofsync1_i_out & tile0_rxlossofsync0_i_out ; TO_USB_READ2 <= tile1_rxbufstatus1_i_out & tile1_rxbufstatus0_i_out & tile0_rxbufstatus1_i_out & tile0_rxbufstatus0_i_out & RXRUNDISP1_4 & RXRUNDISP0_3 & RXRUNDISP1_2 & RXRUNDISP0_1 & RXSTATUS1_4 & RXSTATUS0_3 & RXSTATUS1_2 & RXSTATUS0_1; TO_USB_READ3 <= TXBUFSTATUS1_4 & TXBUFSTATUS0_3 & TXBUFSTATUS1_2 & TXBUFSTATUS0_1 & TXRUNDISP1_4 & TXRUNDISP0_3 & TXRUNDISP1_2 & TXRUNDISP0_1 & TXKERR1_4 & TXKERR0_3 & TXKERR1_2 & TXKERR0_1 & tile1_rxcharisk1_i & tile1_rxcharisk0_i & tile0_rxcharisk1_i & tile0_rxcharisk0_i; TO_USB_READ4 <= tile1_rxcommadet1_i_out & tile1_rxcommadet0_i_out & tile0_rxcommadet1_i_out & tile0_rxcommadet0_i_out & X"0" & tile1_rxbyterealign1_i_out & tile1_rxbyterealign0_i_out & tile0_rxbyterealign1_i_out & tile0_rxbyterealign0_i_out & tile1_rxbyteisaligned1_i_out & tile1_rxbyteisaligned0_i_out & tile0_rxbyteisaligned1_i_out & tile0_rxbyteisaligned0_i_out & tile1_rxchanrealign1_i_out & tile1_rxchanrealign0_i_out & tile0_rxchanrealign1_i_out & tile0_rxchanrealign0_i_out & tile1_rxchanisaligned1_i_out & tile1_rxchanisaligned0_i_out & tile0_rxchanisaligned1_i_out & tile0_rxchanisaligned0_i_out & -- tile1_resetdone1_i_out & tile1_resetdone0_i_out & -- tile0_resetdone1_i_out & tile0_resetdone0_i_out & RXPRBSERR1_4 & RXPRBSERR0_3 & RXPRBSERR1_2 & RXPRBSERR0_1 & rxelecidle1_4 & rxelecidle0_3 & rxelecidle1_2 & rxelecidle0_1; -- -- TO_USB_READ5 <= X"000" & "00000" & PHYSTATUS1_4 & PHYSTATUS0_3 & PHYSTATUS1_2 & PHYSTATUS0_1 & rxrecclk_dcm4_locked_out & rxrecclk_dcm3_locked_out & rxrecclk_dcm0_locked_out & rxrecclk_dcm1_locked_out & refclkout_pll5_locked_out & refclkout_pll2_locked_out & -- tile1_clkdet_i & tile0_clkdet_i & tile0_plllkdet_i & tile0_plllkdet_i & mgtreset & GLOBAL_RESET & USB_RST; ------------------ MGTTXP0_112 <= txp_out_i(0); MGTTXN0_112 <= txn_out_i(0); rxp_in_i(0) <= MGTRXP0_112; rxn_in_i(0) <= MGTRXN0_112; rxn_in_i(1) <= MGTRXN1_112; rxp_in_i(1) <= MGTRXP1_112; MGTTXN1_112 <= txn_out_i(1); MGTTXP1_112 <= txp_out_i(1); MGTTXP0_116 <= txp_out_i(2); MGTTXN0_116 <= txn_out_i(2); rxp_in_i(2) <= MGTRXP0_116; rxn_in_i(2) <= MGTRXN0_116; rxn_in_i(3) <= MGTRXN1_116; rxp_in_i(3) <= MGTRXP1_116; MGTTXN1_116 <= txn_out_i(3); MGTTXP1_116 <= txp_out_i(3); ------------------------------------------------------------------- --de-packetization packRX1: agfo_mgt_receiver PORT MAP ( rst => GLOBAL_RESET, --TILE0RX_RST0, --RST, RX_RST => GLOBAL_RESET, --TILE0RX_RST0, -- clk_125 => tile0_rxclk0_i, clk_125 => tile1_rxclk0_i, clk_165 => clk_in, -- data_in => tile0_rxdata0_i, data_in => tile1_rxdata0_i, -- charisk => tile0_rxcharisk0_i, charisk => tile1_rxcharisk0_i, chselreg => no_ch_fibre1, regceb_out => regceb_out_F1, valid_data => VALID_EN_F1, data_out => data_out_F1, node_seq_reg => node_seq_reg_F1, RxSeq => RxSeq_F1 ); RX_SYNC <= '1' when RxSeq_F1 = 0 else '0'; process(tile1_rxclk0_i) begin if tile1_rxclk0_i'event and tile1_rxclk0_i = '1' then RX_SYNCL1 <= RX_SYNC; end if; end process; --process(tile0_rxclk0_i) --begin -- if tile0_rxclk0_i'event and tile0_rxclk0_i = '1' then ---- if(reset = '1') then -- if GLOBAL_RESET = '1' then -- check_ld_low1 <= '0'; -- rx_slide1 <= '0'; -- end if; -- RXRESET0_IN1_L1 <= RXRESET0_IN1; -- if RXRESET0_IN1_L1 = '1' and check_ld_low1 = '0' then -- rx_slide1 <= '1'; -- check_ld_low1 <= '1'; -- elsif RXRESET0_IN1_L1 = '1' and check_ld_low1 = '1' then -- rx_slide1 <= rx_slide1 ; -- check_ld_low1 <= check_ld_low1; -- elsif RXRESET0_IN1_L1 = '0' and check_ld_low1 = '1' then -- check_ld_low1<= '0'; -- rx_slide1 <= rx_slide1; -- elsif RXRESET0_IN1_L1 = '0' and check_ld_low1 = '0' then -- rx_slide1 <= rx_slide1 ; -- check_ld_low1<= '0';--check_ld_low; -- end if; -- if rx_slide1 = '1' then -- rx_slide1 <= '0'; -- end if; -- end if; --end process; packRX2: agfo_mgt_receiver PORT MAP ( rst => GLOBAL_RESET, --TILE0RX_RST1, --RST, RX_RST => GLOBAL_RESET, --TILE0RX_RST1, -- clk_125 => tile0_rxclk1_i, clk_125 => tile0_rxclk0_i, clk_165 => clk_in, -- data_in => tile0_rxdata1_i, data_in => tile0_rxdata0_i, -- charisk => tile0_rxcharisk1_i, charisk => tile0_rxcharisk0_i, chselreg => no_ch_fibre2, regceb_out => regceb_out_F2, valid_data => VALID_EN_F2, data_out => data_out_F2, node_seq_reg => node_seq_reg_F2, RxSeq => RxSeq_F2 ); -- --process(tile0_rxclk1_i) --begin -- if tile0_rxclk1_i'event and tile0_rxclk1_i = '1' then ---- if(reset = '1') then -- if GLOBAL_RESET = '1' then -- check_ld_low2 <= '0'; -- rx_slide2 <= '0'; -- end if; -- RXRESET0_IN1_L2 <= RXRESET0_IN2; -- if RXRESET0_IN1_L2 = '1' and check_ld_low2 = '0' then -- rx_slide2 <= '1'; -- check_ld_low2 <= '1'; -- elsif RXRESET0_IN1_L2 = '1' and check_ld_low2 = '1' then -- rx_slide2 <= rx_slide2 ; -- check_ld_low2 <= check_ld_low2; -- elsif RXRESET0_IN1_L2 = '0' and check_ld_low2 = '1' then -- check_ld_low2<= '0'; -- rx_slide2 <= rx_slide2; -- elsif RXRESET0_IN1_L2 = '0' and check_ld_low2 = '0' then -- rx_slide2 <= rx_slide2 ; -- check_ld_low2<= '0';--check_ld_low; -- end if; -- if rx_slide2 = '1' then -- rx_slide2 <= '0'; -- end if; -- end if; --end process; packRX3: agfo_mgt_receiver PORT MAP ( rst => GLOBAL_RESET, --TILE1RX_RST0, --RST, RX_RST => GLOBAL_RESET, --TILE1RX_RST0, -- clk_125 => tile1_rxclk0_i, clk_125 => tile0_rxclk1_i, clk_165 => clk_in, -- data_in => tile1_rxdata0_i, data_in => tile0_rxdata1_i, -- charisk => tile1_rxcharisk0_i, charisk => tile0_rxcharisk1_i, chselreg => no_ch_fibre3, regceb_out => regceb_out_F3, valid_data => VALID_EN_F3, data_out => data_out_F3, node_seq_reg => node_seq_reg_F3, RxSeq => RxSeq_F3 ); --process(tile1_rxclk0_i) --begin -- if tile1_rxclk0_i'event and tile1_rxclk0_i = '1' then ---- if(reset = '1') then -- if GLOBAL_RESET = '1' then -- check_ld_low3 <= '0'; -- rx_slide3 <= '0'; -- -- end if; -- RXRESET0_IN1_L3 <= RXRESET0_IN3; -- if RXRESET0_IN1_L3 = '1' and check_ld_low3 = '0' then -- rx_slide3 <= '1'; -- check_ld_low3 <= '1'; -- elsif RXRESET0_IN1_L3 = '1' and check_ld_low3 = '1' then -- rx_slide3 <= rx_slide3 ; -- check_ld_low3 <= check_ld_low3; -- elsif RXRESET0_IN1_L3 = '0' and check_ld_low3 = '1' then -- check_ld_low3<= '0'; -- rx_slide3 <= rx_slide3; -- elsif RXRESET0_IN1_L3 = '0' and check_ld_low3 = '0' then -- rx_slide3 <= rx_slide3 ; -- check_ld_low3<= '0';--check_ld_low; -- end if; -- if rx_slide3 = '1' then -- rx_slide3 <= '0'; -- end if; -- end if; --end process; packRX4: agfo_mgt_receiver PORT MAP ( rst => GLOBAL_RESET, --TILE1RX_RST1, --RST, RX_RST => GLOBAL_RESET, --TILE1RX_RST1, clk_125 => tile1_rxclk1_i, clk_165 => clk_in, data_in => tile1_rxdata1_i, charisk => tile1_rxcharisk1_i, chselreg => no_ch_fibre4, regceb_out => regceb_out_F4, valid_data => VALID_EN_F4, data_out => data_out_F4, node_seq_reg => node_seq_reg_F4, RxSeq => RxSeq_F4 ); --process(tile1_rxclk1_i) --begin -- if tile1_rxclk1_i'event and tile1_rxclk1_i = '1' then ---- if(reset = '1') then -- if GLOBAL_RESET = '1' then -- check_ld_low4 <= '0'; -- rx_slide4 <= '0'; -- -- end if; -- RXRESET0_IN1_L4 <= RXRESET0_IN4; -- if RXRESET0_IN1_L4 = '1' and check_ld_low4 = '0' then -- rx_slide4 <= '1'; -- check_ld_low4 <= '1'; -- elsif RXRESET0_IN1_L4 = '1' and check_ld_low4 = '1' then -- rx_slide4 <= rx_slide4 ; -- check_ld_low4 <= check_ld_low4; -- elsif RXRESET0_IN1_L4 = '0' and check_ld_low4 = '1' then -- check_ld_low4<= '0'; -- rx_slide4 <= rx_slide4; -- elsif RXRESET0_IN1_L4 = '0' and check_ld_low4 = '0' then -- rx_slide4 <= rx_slide4 ; -- check_ld_low4<= '0';--check_ld_low; -- end if; -- if rx_slide4 = '1' then -- rx_slide4 <= '0'; -- end if; -- end if; --end process; ----------------------------------------------------------------- select_data : process(clk_in) begin if clk_in'event and clk_in = '1' then if FIBRE_BKPLN_SEL = '0' then -- FROM backplane DATA_TO_VSIB <= din; -- 160-bit data direct to VSIB REGCEB_TO_VSIB <= regceb; VALID_EN_TO_VSIB <= valid_enable; no_of_chns_TO_VSIB <= ch_sel_reg; -- ch_sel_reg_fiber_VSIB <= ch_sel_reg_fiber;--ch_sel_reg; else if VSIB_FIBRE_NUM = "00" then DATA_TO_VSIB <= data_out_F1; REGCEB_TO_VSIB <= regceb_out_F1; VALID_EN_TO_VSIB <= VALID_EN_F1; no_of_chns_TO_VSIB <= "00000" & no_ch_fibre1; -- ch_sel_reg_fiber_VSIB <= ch_sel_reg_fiber; elsif VSIB_FIBRE_NUM = "01" then DATA_TO_VSIB <= data_out_F1; --data_out_F2; REGCEB_TO_VSIB <= regceb_out_F1; --regceb_out_F2; VALID_EN_TO_VSIB <= VALID_EN_F1; --VALID_EN_F2; no_of_chns_TO_VSIB <= "00000" & no_ch_fibre2; -- ch_sel_reg_fiber_VSIB <= ch_sel_reg_fiber; elsif VSIB_FIBRE_NUM = "10" then DATA_TO_VSIB <= data_out_F1; --data_out_F3; REGCEB_TO_VSIB <= regceb_out_F1; --regceb_out_F3; VALID_EN_TO_VSIB <= VALID_EN_F1; --VALID_EN_F3; no_of_chns_TO_VSIB <= "00000" & no_ch_fibre3; -- ch_sel_reg_fiber_VSIB <= ch_sel_reg_fiber; elsif VSIB_FIBRE_NUM = "11" then DATA_TO_VSIB <= data_out_F1; --data_out_F4; REGCEB_TO_VSIB <= regceb_out_F1; --regceb_out_F4; VALID_EN_TO_VSIB <= VALID_EN_F1; --VALID_EN_F4; no_of_chns_TO_VSIB <= "00000" & no_ch_fibre4; -- ch_sel_reg_fiber_VSIB <= ch_sel_reg_fiber; end if; end if; end if; end process; ----------------------------------------------------------------- --select_data : process(clk_in) -- begin -- if clk_in'event and clk_in = '1' then -- -- if FIBRE_BKPLN_SEL = '0' then -- FROM backplane -- DATA_TO_VSIB <= din; -- 160-bit data direct to VSIB -- REGCEB_TO_VSIB <= regceb; -- VALID_EN_TO_VSIB <= valid_enable; -- no_of_chns_TO_VSIB <= ch_sel_reg; -- else -- if ch_sel_reg_out < 8 then -- DATA_TO_VSIB <= data_out_F1; -- REGCEB_TO_VSIB <= regceb_out_F1; -- VALID_EN_TO_VSIB <= VALID_EN_F1; -- no_of_chns_TO_VSIB <= "00000" & no_ch_fibre1; -- elsif ch_sel_reg_out > 7 and ch_sel_reg_out < 16 then -- DATA_TO_VSIB <= data_out_F2; -- REGCEB_TO_VSIB <= regceb_out_F2; -- VALID_EN_TO_VSIB <= VALID_EN_F2; -- no_of_chns_TO_VSIB <= "00000" & no_ch_fibre2; -- elsif ch_sel_reg_out > 15 and ch_sel_reg_out < 24 then -- DATA_TO_VSIB <= data_out_F3; -- REGCEB_TO_VSIB <=regceb_out_F3; -- VALID_EN_TO_VSIB <= VALID_EN_F3; -- no_of_chns_TO_VSIB <= "00000" & no_ch_fibre3; -- elsif ch_sel_reg_out > 23 and ch_sel_reg_out < 32 then -- DATA_TO_VSIB <= data_out_F4; -- REGCEB_TO_VSIB <=regceb_out_F4; -- VALID_EN_TO_VSIB <= VALID_EN_F4; -- no_of_chns_TO_VSIB <= "00000" & no_ch_fibre4; -- end if; -- end if; -- end if; -- end process; ------------ Output FIFO Instantation --------------------------- op_fifo_inst1 : op_fifo1 Port map ( reset => GLOBAL_RESET, --RST, USB_RST => USB_RST, rd_clk_in => fifo_rd_clk, wr_clk_in => clk_in, sctn_in => sctn_clk, fout_in => fout_clk, -- rd_addr_inc_out => rd_addr_inc, burst_mode_in => burst_mode, ch_sel_mode_in => ch_sel_mode, data_in => DATA_TO_VSIB, regceb => REGCEB_TO_VSIB, burst_rd_complete_in => burst_rd_complete, valid_data => VALID_EN_TO_VSIB, channel_no => no_of_chns_TO_VSIB, --ch_sel_reg, ch_sel_reg => ch_sel_reg_fiber, dinL1_out => dinL1_out, regcebL1_out => regcebL1_out, fifo_rd_er_flag_out => fifo_rd_er_flag, vsib_pvalid_out => vsib_pvalid, vsib_trigger_out => vsib_trigger, read_start_out => read_start, read_started_out => read_started, mux1_out => vsib_data, regceb_flag_MON => regceb_flag_MON ); -- ----packetization --gp_lines(0) <= data_load_MON; --gp_lines(1) <= valid_enableL1_MON; ------depacketization --gp_lines(2) <= regceb_flag_MON; --gp_lines(3) <= REGCEB_TO_VSIB; --gp_lines(4) <= VALID_EN_TO_VSIB; -- --gp_lines(5) <= GLOBAL_RESET; --gp_lines(6) <= mgtreset; --gp_lines(7) <= USB_RST; -- -- --t0_txcharisk0(0) <= tile0_txcharisk0_i(0); --t0_txcharisk0(1) <= tile0_txcharisk0_i(1); -- --t0_txcharisk1(0) <= tile0_txcharisk1_i(0); --t0_txcharisk1(1) <= tile0_txcharisk1_i(1); -- --t1_txcharisk0(0) <= tile1_txcharisk0_i(0); --t1_txcharisk0(1) <= tile1_txcharisk0_i(1); -- -- --t1_txcharisk1(0) <= tile1_txcharisk1_i(0); --t1_txcharisk1(1) <= tile1_txcharisk1_i(1); -- ---------------------------------------------- --t0_rxcharisk0(0) <= tile0_rxcharisk0_i(0); --t0_rxcharisk0(1) <= tile0_rxcharisk0_i(1); -- --t0_rxcharisk1(0) <= tile0_rxcharisk1_i(0); --t0_rxcharisk1(1) <= tile0_rxcharisk1_i(1); -- --t1_rxcharisk0(0) <= tile1_rxcharisk0_i(0); --t1_rxcharisk0(1) <= tile1_rxcharisk0_i(1); -- --t1_rxcharisk1(0) <= tile1_rxcharisk1_i(0); --t1_rxcharisk1(1) <= tile1_rxcharisk1_i(1); ------------------------------------------------- --nu1 <= '0'; --nu2 <= '0'; --nu3 <= '0'; --nu4 <= '0'; ------------------------------------------------------------------- op_module_inst1 : op_module1 Port map ( data_in => vsib_data, rd_clk_in => fifo_rd_clk, reset_in => GLOBAL_RESET, --RST, vsib_pvalid_in => vsib_pvalid, vsib_trigger_in => vsib_trigger, DAS_OP_P => DAS_OP_P, DAS_OP_N => DAS_OP_N, DAS_trigger_P => DAS_trigger_P, DAS_trigger_N => DAS_trigger_N, DAS_clk_P => DAS_clk_P, DAS_clk_N => DAS_clk_N, DAS_pvalid_P => DAS_pvalid_P, DAS_pvalid_N => DAS_pvalid_N ); -- -- --op_module_inst1 : op_module2a -- Port map ( -- data_in => vsib_data, -- rd_clk_in => fifo_rd_clk, -- reset_in => GLOBAL_RESET, -- vsib_pvalid_in => vsib_pvalid, -- vsib_trigger_in => vsib_trigger, -- -- lv1_n => lv1_n, -- lv1_p => lv1_p, -- lv2_n => lv2_n, -- lv2_p => lv2_p, -- lv3_n => lv3_n, -- lv3_p => lv3_p, -- lv4_n => lv4_n, -- lv4_p => lv4_p, -- lv5_n => lv5_n, -- lv5_p => lv5_p, -- lv6_n => lv6_n, -- lv6_p => lv6_p, -- lv7_n => lv7_n, -- lv7_p => lv7_p, -- lv8_n => lv8_n, -- lv8_p => lv8_p, -- lv9_n => lv9_n, -- lv9_p => lv9_p, -- lv10_n => lv10_n, -- lv10_p => lv10_p, -- lv11_n => lv11_n, -- lv11_p => lv11_p, -- lv12_n => lv12_n, -- lv12_p => lv12_p, -- lv65_n => lv65_n, -- lv65_p => lv65_p -- ); -- clk165_out : OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map ( O => gc8_p, -- Diff_p output (connect directly to top-level port) OB => gc8_n, -- Diff_n output (connect directly to top-level port) I => SCTN_L1 -- Buffer input -- CORRECT ONE - 20032008 ); sctn_out : OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map ( O => extck2_p, -- Diff_p output (connect directly to top-level port) OB => extck2_n, -- Diff_n output (connect directly to top-level port) I => clk_in -- Buffer input -- CORRECT ONE - 20032008 ); --TO BE PUT BACK --lv63_P <= SCTN_DELAYED; --regceb; --lv63_N <= SCTN_L1; --valid_enable; lv63_P <= SCTN_DELAYED; --regceb; lv63_N <= SCTN_L1; --valid_enable; lv65_P <= RX_SYNCL1; --regceb_flag_MON; lv65_N <= fout_clk; gc10_p <= tile1_rxnotintable0_i_out(1) or tile1_rxnotintable0_i_out(0); gc10_n <= tile0_rxnotintable0_i_out(1) or tile0_rxnotintable0_i_out(0); gc11_p <= tile1_rxnotintable0_i_out(1) or tile1_rxnotintable0_i_out(0); ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- end Behavioral; ------------- end of file : agfo12_b.vhd -------------------------