The signal <An<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM_ADV comp fifo_clock_gen/DCM_BASE_inst/fifo_clock_gen/DCM_BASE_inst, consult the device Data Sheet. A non-integer value 5.5 was specified for CLKDV_DIVIDE while in high frequency mode. The CLKDV output will have slightly less than a 50/50 duty cycle. A non-integer value 5.5 was specified for CLKDV_DIVIDE while in high frequency mode. The CLKDV output will have slightly less than a 50/50 duty cycle.