Logical network An<2>_IBUF has no load. The above warning message base_net_load_rule is repeated 21 more times for the following (max. 5 shown): sim_reset_mgt_model_i/U1/ROC, usb_if_inst1/dp1/BU2/N2, op_fifo_inst1/fifo_inst1/rd_data_count<6>, op_fifo_inst1/fifo_inst1/rd_data_count<5>, op_fifo_inst1/fifo_inst1/rd_data_count<4> To see the details of these warning messages, please use the -detail switch. No environment variables are currently set. PLL_ADV example_mgt_top_i/refclkout_pll2_i/pll_adv_i CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin. PLL_ADV example_mgt_top_i/refclkout_pll5_i/pll_adv_i CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin. Changing COMPENSATION attribute from SYSTEM_SYNCHRONOUS to INTERNAL for PLL_ADV example_mgt_top_i/refclkout_pll2_i/pll_adv_i. Changing COMPENSATION attribute from SYSTEM_SYNCHRONOUS to INTERNAL for PLL_ADV example_mgt_top_i/refclkout_pll5_i/pll_adv_i. All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. trimming timing constraints from power/ground net example_mgt_top_i/rocketio_wrapper_i/tile0_txcharisk0_r<1> trimming timing constraints from power/ground net example_mgt_top_i/rocketio_wrapper_i/tile0_txcharisk1_r<1> trimming timing constraints from power/ground net example_mgt_top_i/rocketio_wrapper_i/tile1_txcharisk0_r<1> trimming timing constraints from power/ground net example_mgt_top_i/rocketio_wrapper_i/tile1_txcharisk1_r<1> The register FDCPE_sctn_inst1 has the property IOB=TRUE, but was not packed into the OLOGIC component. The output signal for register symbol FDCPE_sctn_inst1 requires general routing. The register FDCPE_sctn_inst1 has the property IOB=TRUE, but was not packed into the OLOGIC component. The output signal for register symbol FDCPE_sctn_inst1 requires general routing. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) Map created a placed design. This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report. N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. The signal <An<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM_ADV comp fifo_clock_gen/DCM_BASE_inst/fifo_clock_gen/DCM_BASE_inst, consult the device Data Sheet.