---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:59:00 04/16/2008 - KPA -- Design Name: -- Module Name: agfo_bkpl_inputs - Behavioral -- Project Name: ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity agfo_bkpl_inputs_C1_P1P2 is Port ( clk_in : in std_logic; clk200 : in std_logic; delay_ce : in std_logic; delay_inc_dec : in std_logic; RESET_IN : in std_logic; LRST1 : in std_logic; deser_command_in : in std_logic; data_ready_mux_A1: in std_logic; data_in : in std_logic_vector(4 downto 0); load_pulse : out std_logic; data_ready_C1 : out std_logic; A1_Ldata_P1 : out std_logic_vector(9 downto 0); A1_Ldata_P2 : out std_logic_vector(9 downto 0) ); end agfo_bkpl_inputs_C1_P1P2; architecture Behavioral of agfo_bkpl_inputs_C1_P1P2 is signal flag, mux_ctrl, mux_ctrl_in, data_ready_in_A1,data_ready, A1_clkbufg : std_logic; signal data_ready1,load_pulse_1 : std_logic; signal A1_data, A1_data_P1, A1_data_P2, A1_Ldata : std_logic_vector(9 downto 0) ; signal data_ready_mux_C1, mux_ctrl_in_A1,data_ready_mux_toiddr, data_ready_in,clk_in_delay : std_logic; signal data_to_iddr : std_logic_vector(4 downto 0); begin ---------------------------------------------------------------------- -------------------------------------------------------------------- IDELAY_inst_clkC1 : IDELAY generic map ( IOBDELAY_TYPE => "VARIABLE", -- "DEFAULT", "FIXED" or "VARIABLE" IOBDELAY_VALUE => 0) -- Any value from 0 to 63 port map ( O => clk_in_delay, -- 1-bit output C => clk200, -- 1-bit clock input CE => delay_ce, -- 1-bit clock enable input I => clk_in, -- 1-bit data input INC => delay_inc_dec, -- 1-bit increment input RST => LRST1-- 1-bit reset input ); -------------------------------------------------------------------- ----######### delays for the i/p data ############## IDELAY_inst_dataC1: FOR i IN 0 to 4 GENERATE BEGIN IDELAY_inst : IDELAY generic map ( IOBDELAY_TYPE => "FIXED", -- "DEFAULT", "FIXED" or "VARIABLE" IOBDELAY_VALUE => 38) -- Any value from 0 to 63 port map ( O => data_to_iddr(i), -- 1-bit output C => '0', -- 1-bit clock input CE => '0', -- 1-bit clock enable input I => data_in(i), -- 1-bit data input INC => '0', -- 1-bit increment input RST => '0' -- 1-bit reset input ); END GENERATE; IDELAY_inst_drC1 : IDELAY generic map ( IOBDELAY_TYPE => "FIXED", -- "DEFAULT", "FIXED" or "VARIABLE" IOBDELAY_VALUE => 38) -- Any value from 0 to 63 port map ( O => data_ready_mux_toiddr, -- 1-bit output C => '0', -- 1-bit clock input CE => '0', -- 1-bit clock enable input I => data_ready_mux_A1, -- 1-bit data input INC => '0', -- 1-bit increment input RST => '0' -- 1-bit reset input ); ----------------------------------------------------------------------- ------******** IDDRs for backplane Inputs *********** IDDR_inst0: FOR i IN 0 to 4 GENERATE BEGIN IDDR_inst_i : IDDR generic map ( DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE", "SAME_EDGE" -- or "SAME_EDGE_PIPELINED" INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' SRTYPE => "ASYNC") -- Set/Reset type: "SYNC" or "ASYNC" port map ( Q1 => A1_data(i), -- 1-bit output for positive edge of clock Q2 => A1_data(i+5), -- 1-bit output for negative edge of clock C => A1_clkbufg, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D => data_to_iddr(i), --data_in(i), -- 1-bit DDR data input R => RESET_IN, -- 1-bit reset S => '0' -- 1-bit set ); END GENERATE; IDDR_inst1 : IDDR generic map ( DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE", "SAME_EDGE" -- or "SAME_EDGE_PIPELINED" INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' SRTYPE => "ASYNC") -- Set/Reset type: "SYNC" or "ASYNC" port map ( Q1 => mux_ctrl_in_A1, -- 1-bit output for positive edge of clock Q2 => data_ready_in, -- 1-bit output for negative edge of clock C => A1_clkbufg, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D => data_ready_mux_toiddr, --data_ready_mux_A1, --1-bit DDR data input R => RESET_IN, -- 1-bit reset S => '0' -- 1-bit set ); ------------------------------------------------------------------------------- BUFG_A1_clk_inst1 : BUFG port map ( O => A1_clkbufg, -- Clock buffer output I => clk_in_delay -- Clock buffer input ); ------------------------------------------------------------------------------- PROCESS(A1_clkbufg, mux_ctrl) BEGIN IF A1_clkbufg'event AND A1_clkbufg= '1' THEN IF mux_ctrl = '0' THEN A1_data_P1 <= A1_Ldata; ELSE A1_Ldata_P2 <= A1_Ldata; END IF; A1_Ldata_P1 <= A1_data_P1; END IF; END PROCESS; ------------------------------------------------------------------------------- PROCESS(A1_clkbufg) BEGIN IF A1_clkbufg'EVENT AND A1_clkbufg = '1' THEN IF DESER_COMMAND_IN = '0' THEN mux_ctrl <= NOT data_ready_in; data_ready <= NOT mux_ctrl_in_A1; ELSE mux_ctrl <= NOT mux_ctrl_in_A1; data_ready <= NOT data_ready_in; END IF; A1_Ldata <= A1_data; data_ready1 <= data_ready; data_ready_C1 <= data_ready1; IF data_ready = '1' THEN load_pulse_1 <= not mux_ctrl; ELSE load_pulse <= '0'; END IF; load_pulse <= load_pulse_1; END IF; END PROCESS; END Behavioral;