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-- Create Date:    15:12:14 03/13/2009  -- kpa
-- Design Name: 
-- Module Name:    agfo_mgt_receiver - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity agfo_mgt_receiver is
    Port ( 
           rst         : in  STD_LOGIC;
			  RX_RST      : in  STD_LOGIC;
	        clk_125     : in  STD_LOGIC;
  	        clk_165     : in  STD_LOGIC;
           data_in     : in  STD_LOGIC_VECTOR (15 downto 0);
			  charisk     : in STD_LOGIC_VECTOR (1 downto 0);
			  chselreg    : in  STD_LOGIC_VECTOR (2 downto 0);
  			  regceb_out  : out STD_LOGIC;
           data_out    : out  STD_LOGIC_VECTOR (159 downto 0);
			  node_seq_reg: out  STD_LOGIC_VECTOR (31 downto 0));

end agfo_mgt_receiver;

architecture Behavioral of agfo_mgt_receiver is

signal regceb,chk_flag,rst_latched: std_logic;
signal data_inL1,data_inL2 : std_logic_vector(159 downto 0);
signal header1,header2,header3,checksum,checksum_int : std_logic_vector(15 downto 0);
signal countera : std_logic_vector(4 downto 0);
signal counterb : std_logic_vector(9 downto 0);
signal rst_125,lrst,data_ready,data_latched_125,data_latched,data_ready_165 : std_logic;
signal chsel_cnt : std_logic_vector(2 downto 0);



begin

 process(clk_125)
 begin 
   if clk_125'event and clk_125 = '1' then 
      rst_125 <= RX_RST; --rst;
		data_latched_125 <= data_latched;
      node_seq_reg (15 downto 0)  <= header1;
      node_seq_reg (31 downto 16) <= header2;
	 if rst_125 = '1' then
       countera <= (others => '0');
       counterb <= (others => '0');
		 chsel_cnt <= (others => '0');
		 data_ready <= '0';
		 chk_flag <= '0'; 
 		 checksum <= (others => '0');
--    else
	 elsif (charisk = "00") then 
          if (countera = 0) then
				  countera <= countera + '1';
              header1 <= data_in;
				  checksum <=  checksum xor header1; 
			 elsif (countera = 1 ) then
				 countera <= countera + '1';
             header2 <= data_in;
				 checksum <=  checksum xor header2; 
      	 elsif (countera = 2) then
		       header3 <= data_in;
				 checksum <=  checksum xor header3; 
				 countera <= countera + '1';
			 elsif (countera = 3) then
			    if (chsel_cnt <= chselreg) then
					if (counterb < 9) then
				       counterb <= counterb + '1';
						 if data_latched_125 = '1' then
		                data_ready <= '0';
						 end if;
				   end if;
				   if (counterb = 0) then
				      data_inL1(15 downto 0) <= data_in;
						checksum <=  checksum xor  data_inL1(15 downto 0);
			 	   elsif (counterb = 1) then
				      data_inL1(31 downto 16) <= data_in;
						checksum <=  checksum xor  data_inL1(31 downto 16);
			 	   elsif (counterb = 2) then
				      data_inL1(47 downto 32) <= data_in;
						checksum <=  checksum xor  data_inL1(47 downto 32);
			 	   elsif (counterb = 3) then
				      data_inL1(63 downto 48) <= data_in;
						checksum <=  checksum xor  data_inL1(63 downto 48);
			 	   elsif (counterb = 4) then
				      data_inL1(79 downto 64) <= data_in;
						checksum <=  checksum xor  data_inL1(79 downto 64);
			 	   elsif (counterb = 5) then
				      data_inL1(95 downto 80) <= data_in;
						checksum <=  checksum xor  data_inL1(95 downto 80);
			 	   elsif (counterb = 6) then
				      data_inL1(111 downto 96) <= data_in;
						checksum <=  checksum xor  data_inL1(111 downto 96);
			 	   elsif (counterb = 7) then
				      data_inL1(127 downto 112) <= data_in;
						checksum <=  checksum xor  data_inL1(127 downto 112);
			 	   elsif (counterb = 8) then
				      data_inL1(143 downto 128) <= data_in;
						checksum <=  checksum xor  data_inL1(143 downto 128);
			 	   elsif (counterb = 9) then
                  data_ready <= '1';
				      data_inL1(159 downto 144) <= data_in;
				      data_inL2(159 downto 144) <= data_in;
						data_inL2(143 downto 0) <= data_inL1(143 downto 0);
						checksum <=  checksum xor  data_inL1(159 downto 144);
						counterb <= (others => '0');
                  if (chsel_cnt = chselreg) then
      				    countera <= countera + '1';
    					end if;	
						chsel_cnt <= chsel_cnt + '1';
					end if;	
					
				 end if;
			 elsif (countera = 4) then
                  checksum_int <= data_in;
						if checksum_int = checksum then
						   chk_flag <= '0';
						else 
						   chk_flag <= '1';
						end if;
					countera <= (others => '0') ;
			     if data_latched_125 = '1' then
                 data_ready <= '0';
   		     end if;
		    end if;
	 elsif (charisk = "11")  then
            countera <= (others => '0') ;
			   counterb <= (others => '0');
		      chsel_cnt <= (others => '0');
      	   checksum <= (others => '0');
			   if data_latched_125 = '1' then
               data_ready <= '0';
   		   end if;
	 end if;	
	end if;
end process;
 
process(clk_165)
 begin 
   if clk_165'event and clk_165 = '1' then 
	   data_ready_165 <= data_ready;
		rst_latched <= rst;
      if rst_latched = '1' then
		   regceb <= '0';
		   regceb_out <= '0';
			data_latched <= '0';
      else
        if (data_ready_165 = '1' and data_latched = '0') then
		      data_out <= data_inL2;
			   regceb <= '1';
		      regceb_out <= '1';
			   data_latched <= '1';
			elsif data_ready_165 = '0' then
			      data_latched <= '0';
		   end if;
	      if regceb = '1' then   
	         regceb <= '0';
		      regceb_out <= '0';
        end if;
	   end if;	   
	end if;
end process;
  
 
end Behavioral;