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-- Company: Raman Research Institute
-- Engineer: Deepak Kumar
-- 
-- Create Date:    16:13:22 07/31/2008 
-- Design Name: 
-- Module Name:    clk_gen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity clk_gen is
    Port ( clk : in  STD_LOGIC;
	        clk_lock : out  STD_LOGIC;
           clk_out : out  STD_LOGIC;
           clkdv_out : out  STD_LOGIC);
end clk_gen;

architecture Behavioral of clk_gen is
signal CLK0,CLKFB : STD_LOGIC;
begin
DCM_BASE_inst : DCM_BASE
   generic map (
      CLKDV_DIVIDE => 3.5, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 10.0, -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             --   an integer from 0 to 15
      DFS_FREQUENCY_MODE => "HIGH",   -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE => "HIGH",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
      PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
   port map (
      CLK0 => CLK0,         -- 0 degree DCM CLK ouptput
      CLK180 => open,     -- 180 degree DCM CLK output
      CLK270 => open,     -- 270 degree DCM CLK output
      CLK2X => open,       -- 2X DCM CLK output
      CLK2X180 => open, -- 2X, 180 degree DCM CLK out
      CLK90 => open,       -- 90 degree DCM CLK output
      CLKDV => clkdv_out,       -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => open,       -- DCM CLK synthesis out (M/D)
      CLKFX180 => open, -- 180 degree CLK synthesis out
      LOCKED => clk_lock,     -- DCM LOCK status output
      CLKFB => CLKFB,       -- DCM clock feedback
      CLKIN => clk,       -- Clock input (from IBUFG, BUFG or DCM)
      RST => '0'            -- DCM asynchronous reset input
   );
	
 BUFG_inst : BUFG
   port map (
      O => CLKFB,     -- Clock buffer output
      I => CLK0      -- Clock buffer input
   );

 clk_out <= CLKFB;
end Behavioral;