----------------------------------------------------------------
-- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA
-- File    : usb_command1.vhd 
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.numeric_std.all;

entity delay_command is
    Port (  
    reset_in          : in std_logic;	 
	 usb_data_in   	 : in std_logic_vector(31 downto 0);
	 usb_load_in   	 : in std_logic;
	 clk_in 		       : in std_logic;
	 delay_ce_out      : out std_logic_vector(15 downto 0);
	 delay_ce_out1     : out std_logic_vector(8 downto 0);
	 delay_inc_dec     : out std_logic_vector(15 downto 0)
   );
end delay_command;
-----------------------------------------------------------------
architecture Behavioral of delay_command is

signal usbL1 : std_logic_vector(31 downto 0);
signal delay_command : std_logic_vector(15 downto 0);
signal check_ld_low,usb_load_int,valid_load,lreset : std_logic;

begin

-----------------------------------------------------------------
process(clk_in)
begin
  if clk_in'event and clk_in = '1' then 
     lreset <= reset_in;
   if(lreset = '1') then
	  check_ld_low <= '0';
	  usbL1(31 downto 16) <= X"0000";
--	  delay_inc_dec <= '0';
	  delay_inc_dec <= X"0000";
	else
     usb_load_int <= usb_load_in;
  	   if usb_load_int = '1' and check_ld_low = '0' then
		   valid_load <= '1';
		   check_ld_low <= '1';
	   elsif usb_load_int = '1' and check_ld_low = '1' then 	  
		   valid_load <= valid_load ;
		   check_ld_low <= check_ld_low;
	   elsif usb_load_int = '0' and check_ld_low = '1' then
		     check_ld_low<= '0';
		     valid_load <= valid_load;
	   elsif usb_load_int = '0' and check_ld_low = '0' then		
		     valid_load <= valid_load ;
		  check_ld_low<= '0';--check_ld_low;
    	end if;	  
      if valid_load = '1' then
	    valid_load <= '0';
       usbL1 <= usb_data_in;
      end if;	
--      delay_command <= usbL1(31 downto 16);	
--		if delay_command > X"0000" then
		if (usbL1(31 downto 7) > ("0000000000000000000000000")) then 
		   delay_ce_out <= usbL1(31 downto 16);
			delay_ce_out1 <= usbL1(15 downto 7);						
--	      delay_inc_dec <= usbL1(0);
	      delay_inc_dec <= usbL1(15 downto 0);
			usbL1(31 downto 7) <= "0000000000000000000000000";
	   else
  		   delay_ce_out <= X"0000";
	      delay_inc_dec <= X"0000";
			delay_ce_out1 <= (others => '0');
--	      delay_inc_dec <= '0';
      end if;	
	 end if;	
  end if;
  
end process;

End Behavioral;
--------------- end of file : usb_command1.vhd ------------------