---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:25:11 07/13/2009 -- Design Name: to be used with ADFB -- Module Name: delay_module - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity delay_control_module is Port ( reset_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load_in : in std_logic; clk_in : in std_logic; -- CLK200 -- input_sig : in std_logic; -- lrst : out std_logic; delay_inc_dec1 : out std_logic; delay_inc_dec2 : out std_logic; delay_inc_dec3 : out std_logic; delay_inc_dec4 : out std_logic; delay_ce1 : out std_logic; delay_ce2 : out std_logic; delay_ce3 : out std_logic; delay_ce4 : out std_logic; stop1_mon : out std_logic; i1_mon : out std_logic; usb_load_int_mon : out std_logic; lreset_mon : out std_logic ); end delay_control_module; architecture Behavioral of delay_control_module is signal usbL1 : std_logic_vector(31 downto 0); signal check_ld_low,usb_load_int,valid_load,lreset, sigL1,start_delay : std_logic; signal i1,i2,i3,i4 : std_logic_vector(6 downto 0) := (others=>'0'); signal delay_ce1_int,delay_ce2_int,delay_ce3_int,delay_ce4_int : std_logic; signal stop1,stop2,stop3,stop4 : std_logic; BEGIN ---------------------------------------Latch to 200MHZ-------------------------------------------------- process(clk_in) begin if clk_in'event and clk_in = '1' then lreset <= reset_in; usb_load_int <= usb_load_in; --MONITORING SIGNALS----------------------- lreset_mon <= reset_in; usb_load_int_mon <= usb_load_in; stop1_mon <= stop1; i1_mon <= i1(0); end if; end process; ---------------------------------------USB Loading-------------------------------------------------- process(clk_in) begin if clk_in'event and clk_in = '1' then if(lreset = '1') then check_ld_low <= '0'; else if usb_load_int = '1' and check_ld_low = '0' then valid_load <= '1'; check_ld_low <= '1'; elsif usb_load_int = '1' and check_ld_low = '1' then -- valid_load <= valid_load ; valid_load <= '0' ; check_ld_low <= check_ld_low; elsif usb_load_int = '0' and check_ld_low = '1' then check_ld_low<= '0'; -- valid_load <= valid_load; valid_load <= '0'; elsif usb_load_int = '0' and check_ld_low = '0' then -- valid_load <= valid_load ; valid_load <= '0'; check_ld_low<= '0';--check_ld_low; end if; if valid_load = '1' then -- valid_load <= '0'; usbL1 <= usb_data_in; end if; end if; end if; end process; ---------------------------------------Generate delay controls-------------------------------------------------- process(clk_in) begin if clk_in'event and clk_in = '1' then if(lreset = '1') then i1 <= "0000000"; i2 <= "0000000"; i3 <= "0000000"; i4 <= "0000000"; delay_ce1 <= '0'; delay_ce2 <= '0'; delay_ce3 <= '0'; delay_ce4 <= '0'; delay_ce1_int <= '0'; delay_ce2_int <= '0'; delay_ce3_int <= '0'; delay_ce4_int <= '0'; delay_inc_dec1 <= '0'; delay_inc_dec2 <= '0'; delay_inc_dec3 <= '0'; delay_inc_dec4 <= '0'; stop1 <= '0'; stop2 <= '0'; stop3 <= '0'; stop4 <= '0'; elsif usbL1(31 downto 4) > 0 then -------------------------------------------------------------------------------------------------- if i1 < usbL1(10 downto 4) and stop1 = '0' and delay_ce1_int = '0' then delay_ce1 <= '1'; delay_ce1_int <= '1'; delay_inc_dec1 <= usbL1(0); i1 <= i1 + 1; elsif i1 = usbL1(10 downto 4) and stop1 = '0' and delay_ce1_int = '0' then stop1 <= '1'; delay_ce1 <='0'; delay_ce1_int <='0'; delay_inc_dec1 <='0'; i1 <= "0000000"; end if; -------------------------------------------------------------------------------------------------- if i2 < usbL1(17 downto 11) and stop2 = '0' and delay_ce2_int = '0' then delay_ce2 <= '1'; delay_ce2_int <= '1'; delay_inc_dec2 <= usbL1(1); i2 <= i2 + 1; elsif i2 = usbL1(17 downto 11) and stop2 = '0' and delay_ce2_int = '0' then stop2 <= '1'; delay_ce2 <='0'; delay_ce2_int <='0'; delay_inc_dec2 <='0'; i2 <= "0000000"; end if; -------------------------------------------------------------------------------------------------- if i3 < usbL1(24 downto 18) and stop3 = '0' and delay_ce3_int = '0' then delay_ce3 <= '1'; delay_ce3_int <= '1'; delay_inc_dec3 <= usbL1(2); i3 <= i3 + 1; elsif i3 = usbL1(24 downto 18) and stop3 = '0' and delay_ce3_int = '0' then stop3 <= '1'; delay_ce3 <='0'; delay_ce3_int <='0'; delay_inc_dec3 <='0'; i3 <= "0000000"; end if; -------------------------------------------------------------------------------------------------- if i4 < usbL1(31 downto 25) and stop4 = '0' and delay_ce4_int = '0' then delay_ce4 <= '1'; delay_ce4_int <= '1'; delay_inc_dec4 <= usbL1(3); i4 <= i4 + 1; elsif i4 = usbL1(31 downto 25) and stop4 = '0' and delay_ce4_int = '0' then stop4 <= '1'; delay_ce4 <='0'; delay_ce4_int <='0'; delay_inc_dec4 <='0'; i4 <= "0000000"; end if; -------------------------------------------------------------------------------------------------- else delay_ce1_int <= '0'; delay_ce2_int <= '0'; delay_ce3_int <= '0'; delay_ce4_int <= '0'; delay_ce1 <= '0'; delay_ce2 <= '0'; delay_ce3 <= '0'; delay_ce4 <= '0'; delay_inc_dec1 <= '0'; delay_inc_dec2 <= '0'; delay_inc_dec3 <= '0'; delay_inc_dec4 <= '0'; end if; if delay_ce1_int = '1' then delay_ce1 <= '0'; delay_ce1_int <= '0'; delay_inc_dec1 <= '0'; end if; if delay_ce2_int = '1' then delay_ce2 <= '0'; delay_ce2_int <= '0'; delay_inc_dec2 <= '0'; end if; if delay_ce3_int = '1' then delay_ce3 <= '0'; delay_ce3_int <= '0'; delay_inc_dec3 <= '0'; end if; if delay_ce4_int = '1' then delay_ce4 <= '0'; delay_ce4_int <= '0'; delay_inc_dec4 <= '0'; end if; end if; end process; End Behavioral;