----------------------------------------------------------------
-- Project : delay_load_PULSE_GEN.vhd
-- File    : delay_load_PULSE_GEN.vhd 
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.numeric_std.all;

entity delay_load_PULSE_GEN is
    Port (  
				reset_in          : in std_logic;	 
				clk_in 		      : in std_logic;
				DELAY_ENABLE		: in std_logic;
				DELAY_LOAD_PULSE	: in std_logic;
				usb_command			: in std_logic_vector(31 downto 0);
				
				LOAD_PULSE1			: out std_logic;
				LOAD_PULSE2			: out std_logic;
				LOAD_PULSE3			: out std_logic;
				LOAD_PULSE4			: out std_logic;
				LOAD_PULSE5			: out std_logic;
				LOAD_PULSE6			: out std_logic;
				LOAD_PULSE7			: out std_logic;
				LOAD_PULSE8			: out std_logic;
				LOAD_PULSE9			: out std_logic;
				
				usb_command_L1	   : out std_logic_vector(31 downto 0)
	 
   );
end delay_load_PULSE_GEN;
-----------------------------------------------------------------
architecture Behavioral of delay_load_PULSE_GEN is

signal decode_counter,decode_counterL1 : std_logic_vector(7 downto 0):= (others => '0');
signal DELAY_LOAD_PULSE_L1,DELAY_LOAD_PULSE_L2: std_logic;
signal usb_command_L1_int : std_logic_vector(31 downto 0);

-----------------------------------------------------------------
begin

-----------------------------------------------------------------
process(clk_in)
begin
  if clk_in'event and clk_in = '1' then 	
		DELAY_LOAD_PULSE_L1 <= DELAY_LOAD_PULSE;	  
		DELAY_LOAD_PULSE_L2 <= DELAY_LOAD_PULSE_L1;	 
		usb_command_L1_int <= 	usb_command;		
		usb_command_L1 <= 	usb_command_L1_int;		

		

--		decode_counterL1 <= decode_counter;
	if  reset_in = '1' and DELAY_ENABLE = '0' then
	   decode_counter <= (others => '0');
		LOAD_PULSE1 <= '0';
		LOAD_PULSE2 <= '0';
		LOAD_PULSE3 <= '0';
		LOAD_PULSE4 <= '0';
		LOAD_PULSE5 <= '0';
		LOAD_PULSE6 <= '0';
		LOAD_PULSE7 <= '0';
		LOAD_PULSE8 <= '0';
		LOAD_PULSE9 <= '0';
		DELAY_LOAD_PULSE_L1 <= '0';
		DELAY_LOAD_PULSE_L2 <= '0';
   else

		if	DELAY_ENABLE = '1' and DELAY_LOAD_PULSE = '1' then 
			decode_counter <= decode_counter + '1';
		elsif DELAY_ENABLE = '0' then
			decode_counter <= (others => '0');
		end if ;		
		if decode_counter = 1 then
			LOAD_PULSE1 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 2 then
			LOAD_PULSE2 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 3 then
			LOAD_PULSE3 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 4 then
			LOAD_PULSE4 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 5 then
			LOAD_PULSE5 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 6 then
			LOAD_PULSE6 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 7 then
			LOAD_PULSE7 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 8 then
			LOAD_PULSE8 <= DELAY_LOAD_PULSE_L1;
		elsif  decode_counter = 9 then
			LOAD_PULSE9 <= DELAY_LOAD_PULSE_L1;
			
--		elsif  decode_counter = 10 then
--			decode_counter <= (others => '0');
		end if;
	end if;
 end if;
end process;

End Behavioral;