------------------------------------------------------------------------------ --$Date: 2007/09/20 17:36:34 $ --$RCSfile: example_mgt_top_vhd.ejava,v $ --$Revision: 1.1.2.2 $ ------------------------------------------------------------------------------ -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 1.7 -- \ \ Application : GTP Wizard -- / / Filename : example_mgt_top.vhd -- /___/ /\ Timestamp : -- \ \ / \ -- \___\/\___\ -- -- -- Module EXAMPLE_MGT_TOP -- Generated by Xilinx GTP Wizard library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --***********************************Entity Declaration************************ entity EXAMPLE_MGT_TOP is generic ( EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 0; EXAMPLE_LANE_WITH_START_CHAR : integer := 0; EXAMPLE_WORDS_IN_BRAM : integer := 512; EXAMPLE_SIM_GTPRESET_SPEEDUP : integer := 1; EXAMPLE_SIM_PLL_PERDIV2 : bit_vector:= x"190"; EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets ); port ( TILE0_REFCLK_PAD_N_IN : in std_logic; TILE0_REFCLK_PAD_P_IN : in std_logic; TILE1_REFCLK_PAD_N_IN : in std_logic; TILE1_REFCLK_PAD_P_IN : in std_logic; GTPRESET_IN : in std_logic; TILE0_PLLLKDET_OUT : out std_logic; TILE1_PLLLKDET_OUT : out std_logic; TILE0_CLKDET_OUT : out std_logic; TILE1_CLKDET_OUT : out std_logic; GTP_SYSTEM_RESET : out std_logic; TILE0_RXCLK0_OUT : out std_logic; TILE0_RXCLK1_OUT : out std_logic; TILE1_RXCLK0_OUT : out std_logic; TILE1_RXCLK1_OUT : out std_logic; TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA1_OUT : out std_logic_vector(15 downto 0); RXN_IN : in std_logic_vector(3 downto 0); RXP_IN : in std_logic_vector(3 downto 0); TXN_OUT : out std_logic_vector(3 downto 0); TXP_OUT : out std_logic_vector(3 downto 0); tile0_txcharisk0_i : in std_logic_vector(1 downto 0); tile0_txcharisk1_i : in std_logic_vector(1 downto 0); tile1_txcharisk0_i : in std_logic_vector(1 downto 0); tile1_txcharisk1_i : in std_logic_vector(1 downto 0); tile0_txdata0_i : in std_logic_vector(15 downto 0); tile0_txdata1_i : in std_logic_vector(15 downto 0); tile1_txdata0_i : in std_logic_vector(15 downto 0); tile1_txdata1_i : in std_logic_vector(15 downto 0); txchardispmode1 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval1 : in std_logic_vector (1 downto 0); -- to MGT; txchardispmode2 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval2 : in std_logic_vector (1 downto 0); -- to MGT; txchardispmode3 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval3 : in std_logic_vector (1 downto 0); -- to MGT; txchardispmode4 : in std_logic_vector (1 downto 0); -- to MGT; txchardispval4 : in std_logic_vector (1 downto 0); -- to MGT; TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); tile0_refclk_out : out std_logic; tile1_refclk_out : out std_logic; TILE0TX_RST : out std_logic; TILE1TX_RST : out std_logic; TILE0RX_RST0 : out std_logic; TILE0RX_RST1 : out std_logic; TILE1RX_RST0 : out std_logic; TILE1RX_RST1 : out std_logic; TILE0_TXUSRCLK20_OUT : out std_logic; TILE1_TXUSRCLK20_OUT : out std_logic; refclkout_pll2_locked_out : out std_logic; refclkout_pll5_locked_out : out std_logic; rxrecclk_dcm0_locked_out : out std_logic; rxrecclk_dcm3_locked_out : out std_logic; rxrecclk_dcm1_locked_out : out std_logic; rxrecclk_dcm4_locked_out : out std_logic; RXRESET0_IN1 : in std_logic; RXRESET0_IN2 : in std_logic; RXRESET0_IN3 : in std_logic; RXRESET0_IN4 : in std_logic; TXKERR0_1 : out std_logic_vector(1 downto 0); TXKERR1_2 : out std_logic_vector(1 downto 0); TXKERR0_3 : out std_logic_vector(1 downto 0); TXKERR1_4 : out std_logic_vector(1 downto 0); TXRUNDISP0_1 : out std_logic_vector(1 downto 0); TXRUNDISP1_2 : out std_logic_vector(1 downto 0); TXRUNDISP0_3 : out std_logic_vector(1 downto 0); TXRUNDISP1_4 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_1 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_2 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_3 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_4 : out std_logic_vector(1 downto 0); RXSTATUS0_1 : out std_logic_vector(2 downto 0); RXSTATUS1_2 : out std_logic_vector(2 downto 0); RXSTATUS0_3 : out std_logic_vector(2 downto 0); RXSTATUS1_4 : out std_logic_vector(2 downto 0); PHYSTATUS0_1 : out std_logic; PHYSTATUS1_2 : out std_logic; PHYSTATUS0_3 : out std_logic; PHYSTATUS1_4 : out std_logic; rxelecidle0_1 : out std_logic; rxelecidle1_2 : out std_logic; rxelecidle0_3 : out std_logic; rxelecidle1_4 : out std_logic; RXPRBSERR0_1 : out std_logic; RXPRBSERR1_2 : out std_logic; RXPRBSERR0_3 : out std_logic; RXPRBSERR1_4 : out std_logic; RXRUNDISP0_1 : out std_logic_vector(1 downto 0); RXRUNDISP1_2 : out std_logic_vector(1 downto 0); RXRUNDISP0_3 : out std_logic_vector(1 downto 0); RXRUNDISP1_4 : out std_logic_vector(1 downto 0); tile0_resetdone0_i_out : out std_logic; tile0_resetdone1_i_out : out std_logic; tile1_resetdone0_i_out : out std_logic; tile1_resetdone1_i_out : out std_logic; tile0_refclkout_i_out : out std_logic; tile1_refclkout_i_out : out std_logic; tile0_rxlossofsync0_i_out : out std_logic_vector(1 downto 0); tile0_rxlossofsync1_i_out : out std_logic_vector(1 downto 0); tile1_rxlossofsync0_i_out : out std_logic_vector(1 downto 0); tile1_rxlossofsync1_i_out : out std_logic_vector(1 downto 0); tile0_rxchanrealign0_i_out : out std_logic; tile0_rxchanrealign1_i_out : out std_logic; tile1_rxchanrealign0_i_out : out std_logic; tile1_rxchanrealign1_i_out : out std_logic; tile0_rxchanisaligned0_i_out : out std_logic; tile0_rxchanisaligned1_i_out : out std_logic; tile1_rxchanisaligned0_i_out : out std_logic; tile1_rxchanisaligned1_i_out : out std_logic; tile0_rxbufstatus0_i_out : out std_logic_vector(2 downto 0); tile0_rxbufstatus1_i_out : out std_logic_vector(2 downto 0); tile1_rxbufstatus0_i_out : out std_logic_vector(2 downto 0); tile1_rxbufstatus1_i_out : out std_logic_vector(2 downto 0); tile0_rxcommadet0_i_out : out std_logic; tile0_rxcommadet1_i_out : out std_logic; tile1_rxcommadet0_i_out : out std_logic; tile1_rxcommadet1_i_out : out std_logic; tile0_rxbyterealign0_i_out : out std_logic; tile0_rxbyterealign1_i_out : out std_logic; tile1_rxbyterealign0_i_out : out std_logic; tile1_rxbyterealign1_i_out : out std_logic; tile0_rxbyteisaligned0_i_out : out std_logic; tile0_rxbyteisaligned1_i_out : out std_logic; tile1_rxbyteisaligned0_i_out : out std_logic; tile1_rxbyteisaligned1_i_out : out std_logic; tile0_rxnotintable0_i_out : out std_logic_vector(1 downto 0); tile0_rxnotintable1_i_out : out std_logic_vector(1 downto 0); tile1_rxnotintable0_i_out : out std_logic_vector(1 downto 0); tile1_rxnotintable1_i_out : out std_logic_vector(1 downto 0); tile0_rxdisperr0_i_out : out std_logic_vector(1 downto 0); tile0_rxdisperr1_i_out : out std_logic_vector(1 downto 0); tile1_rxdisperr0_i_out : out std_logic_vector(1 downto 0); tile1_rxdisperr1_i_out : out std_logic_vector(1 downto 0); tile0_rxchariscomma0_i_out : out std_logic_vector(1 downto 0); tile0_rxchariscomma1_i_out : out std_logic_vector(1 downto 0); tile1_rxchariscomma0_i_out : out std_logic_vector(1 downto 0); tile1_rxchariscomma1_i_out : out std_logic_vector(1 downto 0) ); end EXAMPLE_MGT_TOP; architecture RTL of EXAMPLE_MGT_TOP is --**************************Component Declarations***************************** component ROCKETIO_WRAPPER generic ( -- Simulation attributes WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset WRAPPER_SIM_PLL_PERDIV2 : bit_vector:= x"190" -- Set to the VCO Unit Interval time ); port ( --_________________________________________________________________________ --_________________________________________________________________________ --TILE0 (Location) ------------------------ Loopback and Powerdown Ports ---------------------- TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0); TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0); TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE0_RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0); TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ TILE0_RXCHANBONDSEQ0_OUT : out std_logic; TILE0_RXCHANBONDSEQ1_OUT : out std_logic; TILE0_RXENCHANSYNC0_IN : in std_logic; TILE0_RXENCHANSYNC1_IN : in std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- TILE0_RXBYTEISALIGNED0_OUT : out std_logic; TILE0_RXBYTEISALIGNED1_OUT : out std_logic; TILE0_RXBYTEREALIGN0_OUT : out std_logic; TILE0_RXBYTEREALIGN1_OUT : out std_logic; TILE0_RXCOMMADET0_OUT : out std_logic; TILE0_RXCOMMADET1_OUT : out std_logic; TILE0_RXENMCOMMAALIGN0_IN : in std_logic; TILE0_RXENMCOMMAALIGN1_IN : in std_logic; TILE0_RXENPCOMMAALIGN0_IN : in std_logic; TILE0_RXENPCOMMAALIGN1_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE0_RXRECCLK0_OUT : out std_logic; TILE0_RXRECCLK1_OUT : out std_logic; TILE0_RXUSRCLK0_IN : in std_logic; TILE0_RXUSRCLK1_IN : in std_logic; TILE0_RXUSRCLK20_IN : in std_logic; TILE0_RXUSRCLK21_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE0_RXCDRRESET0_IN : in std_logic; TILE0_RXCDRRESET1_IN : in std_logic; TILE0_RXN0_IN : in std_logic; TILE0_RXN1_IN : in std_logic; TILE0_RXP0_IN : in std_logic; TILE0_RXP1_IN : in std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- TILE0_RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0); TILE0_RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0); TILE0_RXCHANISALIGNED0_OUT : out std_logic; TILE0_RXCHANISALIGNED1_OUT : out std_logic; TILE0_RXCHANREALIGN0_OUT : out std_logic; TILE0_RXCHANREALIGN1_OUT : out std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- TILE0_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0); TILE0_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- TILE0_CLKIN_IN : in std_logic; TILE0_GTPRESET_IN : in std_logic; TILE0_PLLLKDET_OUT : out std_logic; TILE0_REFCLKOUT_OUT : out std_logic; TILE0_RESETDONE0_OUT : out std_logic; TILE0_RESETDONE1_OUT : out std_logic; TILE0_TXENPMAPHASEALIGN_IN : in std_logic; TILE0_TXPMASETPHASE_IN : in std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0); TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0); TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0); TILE0_TXUSRCLK0_IN : in std_logic; TILE0_TXUSRCLK1_IN : in std_logic; TILE0_TXUSRCLK20_IN : in std_logic; TILE0_TXUSRCLK21_IN : in std_logic; --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE0_TXN0_OUT : out std_logic; TILE0_TXN1_OUT : out std_logic; TILE0_TXP0_OUT : out std_logic; TILE0_TXP1_OUT : out std_logic; --_________________________________________________________________________ --_________________________________________________________________________ --TILE1 (Location) ------------------------ Loopback and Powerdown Ports ---------------------- TILE1_LOOPBACK0_IN : in std_logic_vector(2 downto 0); TILE1_LOOPBACK1_IN : in std_logic_vector(2 downto 0); TILE1_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE1_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); TILE1_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE1_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE1_RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); TILE1_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); TILE1_RXDISPERR1_OUT : out std_logic_vector(1 downto 0); TILE1_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); TILE1_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ TILE1_RXCHANBONDSEQ0_OUT : out std_logic; TILE1_RXCHANBONDSEQ1_OUT : out std_logic; TILE1_RXENCHANSYNC0_IN : in std_logic; TILE1_RXENCHANSYNC1_IN : in std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- TILE1_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); TILE1_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- TILE1_RXBYTEISALIGNED0_OUT : out std_logic; TILE1_RXBYTEISALIGNED1_OUT : out std_logic; TILE1_RXBYTEREALIGN0_OUT : out std_logic; TILE1_RXBYTEREALIGN1_OUT : out std_logic; TILE1_RXCOMMADET0_OUT : out std_logic; TILE1_RXCOMMADET1_OUT : out std_logic; TILE1_RXENMCOMMAALIGN0_IN : in std_logic; TILE1_RXENMCOMMAALIGN1_IN : in std_logic; TILE1_RXENPCOMMAALIGN0_IN : in std_logic; TILE1_RXENPCOMMAALIGN1_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- TILE1_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE1_RXRECCLK0_OUT : out std_logic; TILE1_RXRECCLK1_OUT : out std_logic; TILE1_RXUSRCLK0_IN : in std_logic; TILE1_RXUSRCLK1_IN : in std_logic; TILE1_RXUSRCLK20_IN : in std_logic; TILE1_RXUSRCLK21_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE1_RXCDRRESET0_IN : in std_logic; TILE1_RXCDRRESET1_IN : in std_logic; TILE1_RXN0_IN : in std_logic; TILE1_RXN1_IN : in std_logic; TILE1_RXP0_IN : in std_logic; TILE1_RXP1_IN : in std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- TILE1_RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0); TILE1_RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0); TILE1_RXCHANISALIGNED0_OUT : out std_logic; TILE1_RXCHANISALIGNED1_OUT : out std_logic; TILE1_RXCHANREALIGN0_OUT : out std_logic; TILE1_RXCHANREALIGN1_OUT : out std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- TILE1_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0); TILE1_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- TILE1_CLKIN_IN : in std_logic; TILE1_GTPRESET_IN : in std_logic; TILE1_PLLLKDET_OUT : out std_logic; TILE1_REFCLKOUT_OUT : out std_logic; TILE1_RESETDONE0_OUT : out std_logic; TILE1_RESETDONE1_OUT : out std_logic; TILE1_TXENPMAPHASEALIGN_IN : in std_logic; TILE1_TXPMASETPHASE_IN : in std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TILE1_TXCHARISK0_IN : in std_logic_vector(1 downto 0); TILE1_TXCHARISK1_IN : in std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- TILE1_TXDATA0_IN : in std_logic_vector(15 downto 0); TILE1_TXDATA1_IN : in std_logic_vector(15 downto 0); TILE1_TXUSRCLK0_IN : in std_logic; TILE1_TXUSRCLK1_IN : in std_logic; TILE1_TXUSRCLK20_IN : in std_logic; TILE1_TXUSRCLK21_IN : in std_logic; --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE1_TXN0_OUT : out std_logic; TILE1_TXN1_OUT : out std_logic; TILE1_TXP0_OUT : out std_logic; TILE1_TXP1_OUT : out std_logic; TXCHARDISPMODE0_1 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1_2 : in std_logic_vector(1 downto 0); TXCHARDISPMODE0_3 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1_4 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0_1 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1_2 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0_3 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1_4 : in std_logic_vector(1 downto 0); RXRESET0_IN1 : in std_logic; RXRESET0_IN2 : in std_logic; RXRESET0_IN3 : in std_logic; RXRESET0_IN4 : in std_logic; TXKERR0_1 : out std_logic_vector(1 downto 0); TXKERR1_2 : out std_logic_vector(1 downto 0); TXKERR0_3 : out std_logic_vector(1 downto 0); TXKERR1_4 : out std_logic_vector(1 downto 0); TXRUNDISP0_1 : out std_logic_vector(1 downto 0); TXRUNDISP1_2 : out std_logic_vector(1 downto 0); TXRUNDISP0_3 : out std_logic_vector(1 downto 0); TXRUNDISP1_4 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_1 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_2 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_3 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_4 : out std_logic_vector(1 downto 0); RXSTATUS0_1 : out std_logic_vector(2 downto 0); RXSTATUS1_2 : out std_logic_vector(2 downto 0); RXSTATUS0_3 : out std_logic_vector(2 downto 0); RXSTATUS1_4 : out std_logic_vector(2 downto 0); PHYSTATUS0_1 : out std_logic; PHYSTATUS1_2 : out std_logic; PHYSTATUS0_3 : out std_logic; PHYSTATUS1_4 : out std_logic; rxelecidle0_1 : out std_logic; rxelecidle1_2 : out std_logic; rxelecidle0_3 : out std_logic; rxelecidle1_4 : out std_logic; RXPRBSERR0_1 : out std_logic; RXPRBSERR1_2 : out std_logic; RXPRBSERR0_3 : out std_logic; RXPRBSERR1_4 : out std_logic; RXRUNDISP0_1 : out std_logic_vector(1 downto 0); RXRUNDISP1_2 : out std_logic_vector(1 downto 0); RXRUNDISP0_3 : out std_logic_vector(1 downto 0); RXRUNDISP1_4 : out std_logic_vector(1 downto 0) ); end component; component MGT_USRCLK_SOURCE generic ( FREQUENCY_MODE : string := "LOW"; PERFORMANCE_MODE : string := "MAX_SPEED" ); port ( DIV1_OUT : out std_logic; DIV2_OUT : out std_logic; DCM_LOCKED_OUT : out std_logic; CLK_IN : in std_logic; DCM_RESET_IN : in std_logic ); end component; component FRAME_GEN generic ( WORDS_IN_BRAM : integer := 256; MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port ( -- User Interface TX_DATA : out std_logic_vector(31 downto 0); TX_CHARISK : out std_logic_vector(3 downto 0); -- System Interface USER_CLK : in std_logic; SYSTEM_RESET : in std_logic ); end component; component FRAME_CHECK generic ( RX_DATA_WIDTH : integer := 16; USE_COMMA : integer := 1; WORDS_IN_BRAM : integer := 256; CONFIG_INDEPENDENT_LANES : integer := 0; START_OF_PACKET_CHAR : std_logic_vector := x"55fb"; MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port ( -- User Interface RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0); RX_ENMCOMMA_ALIGN : out std_logic; RX_ENPCOMMA_ALIGN : out std_logic; RX_ENCHAN_SYNC : out std_logic; -- Control Interface INC_IN : in std_logic; INC_OUT : out std_logic; PATTERN_MATCH_N : out std_logic; RESET_ON_ERROR : in std_logic; -- Error Monitoring ERROR_COUNT : out std_logic_vector(7 downto 0); -- System Interface USER_CLK : in std_logic; SYSTEM_RESET : in std_logic ); end component; component MGT_USRCLK_SOURCE_PLL generic ( MULT : integer := 2; DIVIDE : integer := 2; CLK_PERIOD : real := 8.0; OUT0_DIVIDE : integer := 2; OUT1_DIVIDE : integer := 2; OUT2_DIVIDE : integer := 2; OUT3_DIVIDE : integer := 2 ); port ( CLK0_OUT : out std_logic; CLK1_OUT : out std_logic; CLK2_OUT : out std_logic; CLK3_OUT : out std_logic; CLK_IN : in std_logic; PLL_LOCKED_OUT : out std_logic; PLL_RESET_IN : in std_logic ); end component; component TX_SYNC port ( TXENPMAPHASEALIGN : out std_logic; TXPMASETPHASE : out std_logic; SYNC_DONE : out std_logic; USER_CLK : in std_logic; RESET : in std_logic ); end component; -- Chipscope modules attribute syn_black_box : boolean; attribute syn_noprune : boolean; component shared_vio port ( control : in std_logic_vector(35 downto 0); async_in : in std_logic_vector(31 downto 0); async_out : out std_logic_vector(31 downto 0) ); end component; attribute syn_black_box of shared_vio : component is TRUE; attribute syn_noprune of shared_vio : component is TRUE; component icon port ( control0 : out std_logic_vector(35 downto 0); control1 : out std_logic_vector(35 downto 0); control2 : out std_logic_vector(35 downto 0); control3 : out std_logic_vector(35 downto 0); control4 : out std_logic_vector(35 downto 0); control5 : out std_logic_vector(35 downto 0); control6 : out std_logic_vector(35 downto 0) ); end component; attribute syn_black_box of icon : component is TRUE; attribute syn_noprune of icon : component is TRUE; component ila port ( control : in std_logic_vector(35 downto 0); clk : in std_logic; trig0 : in std_logic_vector(63 downto 0) ); end component; attribute syn_black_box of ila : component is TRUE; attribute syn_noprune of ila : component is TRUE; --component trans_test2 -- Port ( clka : in STD_LOGIC; -- clkb : in STD_LOGIC; -- clkc : in STD_LOGIC; -- rst : in STD_LOGIC; -- dout1 : out STD_LOGIC_VECTOR (15 downto 0); -- dout2 : out STD_LOGIC_VECTOR (15 downto 0); -- dout3 : out STD_LOGIC_VECTOR (15 downto 0); -- char1 : out STD_LOGIC_VECTOR (1 downto 0); -- char2 : out STD_LOGIC_VECTOR (1 downto 0); -- char3 : out STD_LOGIC_VECTOR (1 downto 0); -- fout : out STD_LOGIC; -- valid_regceb : in STD_LOGIC; -- valid_data : in STD_LOGIC_VECTOR (159 downto 0); -- valid_clk : in STD_LOGIC; -- wr_en1_out: out STD_LOGIC; -- wr_en2_out: out STD_LOGIC --); --end component; --***********************************Parameter Declarations******************** constant DLY : time := 1 ns; --************************** Register Declarations **************************** signal ila_in0_r : std_logic_vector(63 downto 0); signal ila_in1_r : std_logic_vector(63 downto 0); signal tile0_resetdone0_r : std_logic; signal tile0_resetdone0_r2 : std_logic; signal tile0_resetdone1_r : std_logic; signal tile0_resetdone1_r2 : std_logic; signal tile1_resetdone0_r : std_logic; signal tile1_resetdone0_r2 : std_logic; signal tile1_resetdone1_r : std_logic; signal tile1_resetdone1_r2 : std_logic; --**************************** Wire Declarations ****************************** -------------------------- MGT Wrapper Wires ------------------------------ --________________________________________________________________________ --________________________________________________________________________ --TILE0 (X0Y3) ------------------------ Loopback and Powerdown Ports ---------------------- signal tile0_loopback0_i : std_logic_vector(2 downto 0); signal tile0_loopback1_i : std_logic_vector(2 downto 0); signal tile0_rxpowerdown0_i : std_logic_vector(1 downto 0); signal tile0_rxpowerdown1_i : std_logic_vector(1 downto 0); signal tile0_txpowerdown0_i : std_logic_vector(1 downto 0); signal tile0_txpowerdown1_i : std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- signal tile0_rxchariscomma0_i : std_logic_vector(1 downto 0); signal tile0_rxchariscomma1_i : std_logic_vector(1 downto 0); -- signal tile0_rxcharisk0_i : std_logic_vector(1 downto 0); -- signal tile0_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile0_rxdisperr0_i : std_logic_vector(1 downto 0); signal tile0_rxdisperr1_i : std_logic_vector(1 downto 0); signal tile0_rxnotintable0_i : std_logic_vector(1 downto 0); signal tile0_rxnotintable1_i : std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ signal tile0_rxchanbondseq0_i : std_logic; signal tile0_rxchanbondseq1_i : std_logic; signal tile0_rxenchansync0_i : std_logic; signal tile0_rxenchansync1_i : std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- signal tile0_rxclkcorcnt0_i : std_logic_vector(2 downto 0); signal tile0_rxclkcorcnt1_i : std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- signal tile0_rxbyteisaligned0_i : std_logic; signal tile0_rxbyteisaligned1_i : std_logic; signal tile0_rxbyterealign0_i : std_logic; signal tile0_rxbyterealign1_i : std_logic; signal tile0_rxcommadet0_i : std_logic; signal tile0_rxcommadet1_i : std_logic; signal tile0_rxenmcommaalign0_i : std_logic; signal tile0_rxenmcommaalign1_i : std_logic; signal tile0_rxenpcommaalign0_i : std_logic; signal tile0_rxenpcommaalign1_i : std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- signal tile0_rxdata0_i : std_logic_vector(15 downto 0); signal tile0_rxdata1_i : std_logic_vector(15 downto 0); signal tile0_rxrecclk0_i : std_logic; signal tile0_rxrecclk1_i : std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ signal tile0_rxcdrreset0_i : std_logic; signal tile0_rxcdrreset1_i : std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- signal tile0_rxbufstatus0_i : std_logic_vector(2 downto 0); signal tile0_rxbufstatus1_i : std_logic_vector(2 downto 0); signal tile0_rxchanisaligned0_i : std_logic; signal tile0_rxchanisaligned1_i : std_logic; signal tile0_rxchanrealign0_i : std_logic; signal tile0_rxchanrealign1_i : std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- signal tile0_rxlossofsync0_i : std_logic_vector(1 downto 0); signal tile0_rxlossofsync1_i : std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- signal tile0_gtpreset_i : std_logic; signal tile0_plllkdet_i : std_logic; signal tile0_refclkout_i : std_logic; signal tile0_resetdone0_i : std_logic; signal tile0_resetdone1_i : std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- signal tile0_txcharisk0_ii : std_logic_vector(1 downto 0); signal tile0_txcharisk1_ii : std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- signal tile0_txdata0_ii : std_logic_vector(15 downto 0); signal tile0_txdata1_ii : std_logic_vector(15 downto 0); -- Additional signal added for packetization of data ----------------------- -- signal tile0_txcharisk0_i : std_logic_vector(1 downto 0); -- signal tile0_txcharisk1_i : std_logic_vector(1 downto 0); -- ------------------ Transmit Ports - TX Data Path interface ----------------- -- signal tile0_txdata0_i : std_logic_vector(15 downto 0); -- signal tile0_txdata1_i : std_logic_vector(15 downto 0); --________________________________________________________________________ --________________________________________________________________________ --TILE1 (X0Y4) ------------------------ Loopback and Powerdown Ports ---------------------- signal tile1_loopback0_i : std_logic_vector(2 downto 0); signal tile1_loopback1_i : std_logic_vector(2 downto 0); signal tile1_rxpowerdown0_i : std_logic_vector(1 downto 0); signal tile1_rxpowerdown1_i : std_logic_vector(1 downto 0); signal tile1_txpowerdown0_i : std_logic_vector(1 downto 0); signal tile1_txpowerdown1_i : std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- signal tile1_rxchariscomma0_i : std_logic_vector(1 downto 0); signal tile1_rxchariscomma1_i : std_logic_vector(1 downto 0); -- signal tile1_rxcharisk0_i : std_logic_vector(1 downto 0); -- signal tile1_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile1_rxdisperr0_i : std_logic_vector(1 downto 0); signal tile1_rxdisperr1_i : std_logic_vector(1 downto 0); signal tile1_rxnotintable0_i : std_logic_vector(1 downto 0); signal tile1_rxnotintable1_i : std_logic_vector(1 downto 0); signal tile0_rxcharisk0_i : std_logic_vector(1 downto 0); signal tile0_rxcharisk1_i : std_logic_vector(1 downto 0); signal tile1_rxcharisk0_i : std_logic_vector(1 downto 0); signal tile1_rxcharisk1_i : std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ signal tile1_rxchanbondseq0_i : std_logic; signal tile1_rxchanbondseq1_i : std_logic; signal tile1_rxenchansync0_i : std_logic; signal tile1_rxenchansync1_i : std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- signal tile1_rxclkcorcnt0_i : std_logic_vector(2 downto 0); signal tile1_rxclkcorcnt1_i : std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- signal tile1_rxbyteisaligned0_i : std_logic; signal tile1_rxbyteisaligned1_i : std_logic; signal tile1_rxbyterealign0_i : std_logic; signal tile1_rxbyterealign1_i : std_logic; signal tile1_rxcommadet0_i : std_logic; signal tile1_rxcommadet1_i : std_logic; signal tile1_rxenmcommaalign0_i : std_logic; signal tile1_rxenmcommaalign1_i : std_logic; signal tile1_rxenpcommaalign0_i : std_logic; signal tile1_rxenpcommaalign1_i : std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- signal tile1_rxdata0_i : std_logic_vector(15 downto 0); signal tile1_rxdata1_i : std_logic_vector(15 downto 0); signal tile1_rxrecclk0_i : std_logic; signal tile1_rxrecclk1_i : std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ signal tile1_rxcdrreset0_i : std_logic; signal tile1_rxcdrreset1_i : std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- signal tile1_rxbufstatus0_i : std_logic_vector(2 downto 0); signal tile1_rxbufstatus1_i : std_logic_vector(2 downto 0); signal tile1_rxchanisaligned0_i : std_logic; signal tile1_rxchanisaligned1_i : std_logic; signal tile1_rxchanrealign0_i : std_logic; signal tile1_rxchanrealign1_i : std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- signal tile1_rxlossofsync0_i : std_logic_vector(1 downto 0); signal tile1_rxlossofsync1_i : std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- signal tile1_gtpreset_i : std_logic; signal tile1_plllkdet_i : std_logic; signal tile1_refclkout_i : std_logic; signal tile1_resetdone0_i : std_logic; signal tile1_resetdone1_i : std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- signal tile1_txcharisk0_ii : std_logic_vector(1 downto 0); signal tile1_txcharisk1_ii : std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- signal tile1_txdata0_ii : std_logic_vector(15 downto 0); signal tile1_txdata1_ii : std_logic_vector(15 downto 0); -------- Additional signals added to attach packeting format ------- -- signal tile1_txcharisk0_i : std_logic_vector(1 downto 0); -- signal tile1_txcharisk1_i : std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- -- signal tile1_txdata0_i : std_logic_vector(15 downto 0); -- signal tile1_txdata1_i : std_logic_vector(15 downto 0); ------------------------------- Global Signals ----------------------------- signal tx_system_reset_c : std_logic; signal tile0_rx_system_reset0_c : std_logic; signal tile0_rxreset0_i : std_logic; signal tile0_txreset0_i : std_logic; signal tile0_rx_system_reset1_c : std_logic; signal tile0_rxreset1_i : std_logic; signal tile0_txreset1_i : std_logic; signal tile1_rx_system_reset0_c : std_logic; signal tile1_rxreset0_i : std_logic; signal tile1_txreset0_i : std_logic; signal tile1_rx_system_reset1_c : std_logic; signal tile1_rxreset1_i : std_logic; signal tile1_txreset1_i : std_logic; signal tied_to_ground_i : std_logic; signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); signal tied_to_vcc_i : std_logic; signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); signal drp_clk_in_i : std_logic; signal txpmasetphase_i : std_logic; signal txenpmaphasealign_i : std_logic; signal tile0_refclkout_bufg_i : std_logic; ----------------------------- User Clocks --------------------------------- signal tile1_rxusrclk20_i : std_logic; signal tile1_txusrclk0_i : std_logic; signal tile0_txusrclk20_i : std_logic; signal tile0_rxusrclk0_i : std_logic; signal tile1_txusrclk20_i : std_logic; signal tile1_rxusrclk1_i : std_logic; signal tile0_rxusrclk21_i : std_logic; signal tile0_rxusrclk20_i : std_logic; signal tile0_rxusrclk1_i : std_logic; signal tile1_rxusrclk21_i : std_logic; signal tile1_rxusrclk0_i : std_logic; signal tile0_txusrclk0_i : std_logic; signal rxrecclk_dcm0_locked_i : std_logic; signal rxrecclk_dcm0_reset_i : std_logic; signal tile0_rxrecclk0_to_dcm_i : std_logic; signal rxrecclk_dcm1_locked_i : std_logic; signal rxrecclk_dcm1_reset_i : std_logic; signal tile1_rxrecclk0_to_dcm_i : std_logic; signal refclkout_pll2_locked_i : std_logic; signal refclkout_pll2_reset_i : std_logic; signal tile1_refclkout_to_cmt_i : std_logic; signal rxrecclk_dcm3_locked_i : std_logic; signal rxrecclk_dcm3_reset_i : std_logic; signal tile0_rxrecclk1_to_dcm_i : std_logic; signal rxrecclk_dcm4_locked_i : std_logic; signal rxrecclk_dcm4_reset_i : std_logic; signal tile1_rxrecclk1_to_dcm_i : std_logic; signal refclkout_pll5_locked_i : std_logic; signal refclkout_pll5_reset_i : std_logic; signal tile0_refclkout_to_cmt_i : std_logic; ----------------------- Frame check/gen Module Signals -------------------- signal tile0_refclk_i : std_logic; signal tile0_matchn0_i : std_logic; signal tile0_txcharisk0_float_i : std_logic_vector(1 downto 0); signal tile0_txdata0_float_i : std_logic_vector(15 downto 0); signal tile0_error_count0_i : std_logic_vector(7 downto 0); signal tile0_frame_check0_reset_i : std_logic; signal tile0_inc_in0_i : std_logic; signal tile0_inc_out0_i : std_logic; signal tile0_matchn1_i : std_logic; signal tile0_txcharisk1_float_i : std_logic_vector(1 downto 0); signal tile0_txdata1_float_i : std_logic_vector(15 downto 0); signal tile0_error_count1_i : std_logic_vector(7 downto 0); signal tile0_frame_check1_reset_i : std_logic; signal tile0_inc_in1_i : std_logic; signal tile0_inc_out1_i : std_logic; signal tile1_refclk_i : std_logic; signal tile1_matchn0_i : std_logic; signal tile1_txcharisk0_float_i : std_logic_vector(1 downto 0); signal tile1_txdata0_float_i : std_logic_vector(15 downto 0); signal tile1_error_count0_i : std_logic_vector(7 downto 0); signal tile1_frame_check0_reset_i : std_logic; signal tile1_inc_in0_i : std_logic; signal tile1_inc_out0_i : std_logic; signal tile1_matchn1_i : std_logic; signal tile1_txcharisk1_float_i : std_logic_vector(1 downto 0); signal tile1_txdata1_float_i : std_logic_vector(15 downto 0); signal tile1_error_count1_i : std_logic_vector(7 downto 0); signal tile1_frame_check1_reset_i : std_logic; signal tile1_inc_in1_i : std_logic; signal tile1_inc_out1_i : std_logic; signal reset_on_data_error_i : std_logic; ------------------------- Sync Module Signals ----------------------------- signal tile0_rx_sync_done0_i : std_logic; signal tile0_reset_rxsync0_c : std_logic; signal tile0_rx_sync_done1_i : std_logic; signal tile0_reset_rxsync1_c : std_logic; signal tile1_rx_sync_done0_i : std_logic; signal tile1_reset_rxsync0_c : std_logic; signal tile1_rx_sync_done1_i : std_logic; signal tile1_reset_rxsync1_c : std_logic; signal tx_sync_done_i : std_logic; signal reset_txsync_c : std_logic; ----------------------- Chipscope Signals --------------------------------- signal shared_vio_control_i : std_logic_vector(35 downto 0); signal tx_data_vio_control0_i : std_logic_vector(35 downto 0); signal rx_data_vio_control0_i : std_logic_vector(35 downto 0); signal ila_control0_i : std_logic_vector(35 downto 0); signal tx_data_vio_control1_i : std_logic_vector(35 downto 0); signal rx_data_vio_control1_i : std_logic_vector(35 downto 0); signal ila_control1_i : std_logic_vector(35 downto 0); signal shared_vio_in_i : std_logic_vector(31 downto 0); signal shared_vio_out_i : std_logic_vector(31 downto 0); signal tx_data_vio_in0_i : std_logic_vector(31 downto 0); signal tx_data_vio_out0_i : std_logic_vector(31 downto 0); signal tx_data_vio_in1_i : std_logic_vector(31 downto 0); signal tx_data_vio_out1_i : std_logic_vector(31 downto 0); signal rx_data_vio_in0_i : std_logic_vector(31 downto 0); signal rx_data_vio_out0_i : std_logic_vector(31 downto 0); signal rx_data_vio_in1_i : std_logic_vector(31 downto 0); signal rx_data_vio_out1_i : std_logic_vector(31 downto 0); signal ila_in0_i : std_logic_vector(63 downto 0); signal ila_in1_i : std_logic_vector(63 downto 0); signal tile0_tx_data_vio_in0_i : std_logic_vector(31 downto 0); signal tile0_tx_data_vio_out0_i : std_logic_vector(31 downto 0); signal tile0_rx_data_vio_in0_i : std_logic_vector(31 downto 0); signal tile0_rx_data_vio_out0_i : std_logic_vector(31 downto 0); signal tile0_ila_in0_i : std_logic_vector(63 downto 0); signal tile0_tx_data_vio_in1_i : std_logic_vector(31 downto 0); signal tile0_tx_data_vio_out1_i : std_logic_vector(31 downto 0); signal tile0_rx_data_vio_in1_i : std_logic_vector(31 downto 0); signal tile0_rx_data_vio_out1_i : std_logic_vector(31 downto 0); signal tile0_ila_in1_i : std_logic_vector(63 downto 0); signal tile1_tx_data_vio_in0_i : std_logic_vector(31 downto 0); signal tile1_tx_data_vio_out0_i : std_logic_vector(31 downto 0); signal tile1_rx_data_vio_in0_i : std_logic_vector(31 downto 0); signal tile1_rx_data_vio_out0_i : std_logic_vector(31 downto 0); signal tile1_ila_in0_i : std_logic_vector(63 downto 0); signal tile1_tx_data_vio_in1_i : std_logic_vector(31 downto 0); signal tile1_tx_data_vio_out1_i : std_logic_vector(31 downto 0); signal tile1_rx_data_vio_in1_i : std_logic_vector(31 downto 0); signal tile1_rx_data_vio_out1_i : std_logic_vector(31 downto 0); signal tile1_ila_in1_i : std_logic_vector(63 downto 0); signal gtpreset_i : std_logic; signal mux_sel_i : std_logic; signal user_tx_reset_i : std_logic; signal user_rx_reset_i : std_logic; signal ila_clk0_i : std_logic; signal ila_clk_mux_out0_i : std_logic; signal ila_clk1_i : std_logic; signal ila_clk_mux_out1_i : std_logic; -- Debugging signal 2008-11-28 signal wr_en2_out_sig : std_logic; --**************************** Main Body of Code ******************************* signal cnt : std_logic_vector( 9 downto 0):=(others => '0'); signal tile0_cnt,tile1_cnt : std_logic_vector( 5 downto 0) := (others => '0'); signal TILE0_TMP_RST,TILE1_TMP_RST : std_logic:='0'; signal TILE0_TMP1_RST,TILE1_TMP1_RST : std_logic:='0'; signal tile0_cnt0,tile0_cnt1 : std_logic_vector( 5 downto 0) := (others => '0'); signal TILE0RX_TMP_RST0,TILE0RX_TMP_RST1: std_logic:='0'; signal TILE0RX_TMP1_RST0,TILE0RX_TMP1_RST1: std_logic:='0'; signal tile1_cnt0,tile1_cnt1 : std_logic_vector( 5 downto 0) := (others => '0'); signal TILE1RX_TMP_RST0,TILE1RX_TMP_RST1: std_logic:='0'; signal TILE1RX_TMP1_RST0,TILE1RX_TMP1_RST1: std_logic:='0'; begin -- Static signal Assigments tied_to_ground_i <= '0'; tied_to_ground_vec_i <= x"0000000000000000"; tied_to_vcc_i <= '1'; tied_to_vcc_vec_i <= x"ff"; -----------------------Dedicated GTP Reference Clock Inputs --------------- -- The dedicated reference clock inputs you selected in the GUI are implemented using -- IBUFDS instances. -- -- In the UCF file for this example design, you will see that each of -- these IBUFDS instances has been LOCed to a particular set of pins. By LOCing to these -- locations, we tell the tools to use the dedicated input buffers to the GTP reference -- clock network, rather than general purpose IOs. To select other pins, consult the -- Implementation chapter of UG196, or rerun the wizard. -- -- This network is the highest performace (lowest jitter) option for providing clocks -- to the GTP transceivers. tile0_refclk_ibufds_i : IBUFDS port map ( O => tile0_refclk_i, I => TILE0_REFCLK_PAD_P_IN, IB => TILE0_REFCLK_PAD_N_IN ); tile0_refclk_out <= tile0_refclk_i; tile1_refclk_ibufds_i : IBUFDS port map ( O => tile1_refclk_i, I => TILE1_REFCLK_PAD_P_IN, IB => TILE1_REFCLK_PAD_N_IN ); tile1_refclk_out <= tile1_refclk_i; ----------------------------------- User Clocks --------------------------- -- The clock resources in this section were added based on userclk source selections on -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks: -- * The userclk and userclk2 for each GTP datapath (TX and RX) must be phase aligned to -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits -- * To minimize clock resources, you can share clocks between GTPs. GTPs using the same frequency -- or multiples of the same frequency can be accomadated using DCMs and PLLs. Use caution when -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all -- the channels using the clock are receiving data from TX channels that share a reference clock -- source with each other. --============================================================================================== ----8jan2010-vani -- comments removed -- rxrecclk_dcm0_bufg_i : BUFG -- port map -- ( -- I => tile0_rxrecclk0_i, -- O => tile0_rxrecclk0_to_dcm_i -- ); -- -- rxrecclk_dcm0_reset_i <= not tile0_plllkdet_i; -- rxrecclk_dcm0_i : MGT_USRCLK_SOURCE -- generic map -- ( -- FREQUENCY_MODE => "HIGH", -- PERFORMANCE_MODE => "MAX_SPEED" -- ) -- port map -- ( -- DIV1_OUT => tile0_rxusrclk0_i, -- DIV2_OUT => tile0_rxusrclk20_i, -- DCM_LOCKED_OUT => rxrecclk_dcm0_locked_i, -- CLK_IN => tile0_rxrecclk0_to_dcm_i, -- DCM_RESET_IN => rxrecclk_dcm0_reset_i -- ); --============================================================================================== rxrecclk_dcm1_bufg_i : BUFG port map ( I => tile1_rxrecclk0_i, O => tile1_rxrecclk0_to_dcm_i ); rxrecclk_dcm1_reset_i <= not tile1_plllkdet_i; rxrecclk_dcm1_i : MGT_USRCLK_SOURCE generic map ( FREQUENCY_MODE => "HIGH", PERFORMANCE_MODE => "MAX_SPEED" ) port map ( DIV1_OUT => tile1_rxusrclk0_i, DIV2_OUT => tile1_rxusrclk20_i, DCM_LOCKED_OUT => rxrecclk_dcm1_locked_i, CLK_IN => tile1_rxrecclk0_to_dcm_i, DCM_RESET_IN => rxrecclk_dcm1_reset_i ); ------------------------------------------------------------------------------------------------- refclkout_pll2_bufg_i : BUFG port map ( I => tile1_refclkout_i, O => tile1_refclkout_to_cmt_i ); refclkout_pll2_reset_i <= not tile1_plllkdet_i; refclkout_pll2_i : MGT_USRCLK_SOURCE_PLL generic map ( MULT => 6, DIVIDE => 1, CLK_PERIOD => 8.0, OUT0_DIVIDE => 6, OUT1_DIVIDE => 3, OUT2_DIVIDE => 1, OUT3_DIVIDE => 1 ) port map ( CLK0_OUT => tile1_txusrclk20_i, CLK1_OUT => tile1_txusrclk0_i, CLK2_OUT => open, CLK3_OUT => open, CLK_IN => tile1_refclkout_to_cmt_i, PLL_LOCKED_OUT => refclkout_pll2_locked_i, PLL_RESET_IN => refclkout_pll2_reset_i ); TILE1_CLKDET_OUT <= tile1_txusrclk20_i; --============================================================================================== ----8jan2010-vani -- comments removed -- rxrecclk_dcm3_bufg_i : BUFG -- port map -- ( -- I => tile0_rxrecclk1_i, -- O => open --tile0_rxrecclk1_to_dcm_i -- ); rxrecclk_dcm3_reset_i <= not tile0_plllkdet_i; -- rxrecclk_dcm3_i : MGT_USRCLK_SOURCE -- generic map -- ( -- FREQUENCY_MODE => "HIGH", -- PERFORMANCE_MODE => "MAX_SPEED" -- ) -- port map -- ( -- DIV1_OUT => tile0_rxusrclk1_i, -- DIV2_OUT => tile0_rxusrclk21_i, -- DCM_LOCKED_OUT => rxrecclk_dcm3_locked_i, -- CLK_IN => tile0_rxrecclk1_to_dcm_i, -- DCM_RESET_IN => rxrecclk_dcm3_reset_i -- ); --============================================================================================== ----8jan2010-vani -- comments removed -- rxrecclk_dcm4_bufg_i : BUFG -- port map -- ( -- I => tile1_rxrecclk1_i, -- O => open --tile1_rxrecclk1_to_dcm_i -- ); rxrecclk_dcm4_reset_i <= not tile1_plllkdet_i; -- rxrecclk_dcm4_i : MGT_USRCLK_SOURCE -- generic map -- ( -- FREQUENCY_MODE => "HIGH", -- PERFORMANCE_MODE => "MAX_SPEED" -- ) -- port map -- ( -- DIV1_OUT => tile1_rxusrclk1_i, -- DIV2_OUT => tile1_rxusrclk21_i, -- DCM_LOCKED_OUT => rxrecclk_dcm4_locked_i, -- CLK_IN => tile1_rxrecclk1_to_dcm_i, -- DCM_RESET_IN => rxrecclk_dcm4_reset_i -- ); --============================================================================================== refclkout_pll5_bufg_i : BUFG port map ( I => tile0_refclkout_i, O => tile0_refclkout_to_cmt_i ); refclkout_pll5_reset_i <= not tile0_plllkdet_i; refclkout_pll5_i : MGT_USRCLK_SOURCE_PLL generic map ( MULT => 6, DIVIDE => 1, CLK_PERIOD => 8.0, OUT0_DIVIDE => 6, OUT1_DIVIDE => 3, OUT2_DIVIDE => 1, OUT3_DIVIDE => 1 ) port map ( CLK0_OUT => tile0_txusrclk20_i, CLK1_OUT => tile0_txusrclk0_i, CLK2_OUT => open, CLK3_OUT => open, CLK_IN => tile0_refclkout_to_cmt_i, PLL_LOCKED_OUT => refclkout_pll5_locked_i, PLL_RESET_IN => refclkout_pll5_reset_i ); TILE0_CLKDET_OUT <= tile0_txusrclk20_i; ----------------------------- The GTP Wrapper ----------------------------- -- Use the instantiation template in the examples directory to add the GTP wrapper to your design. -- In this example, the wrapper is wired up for basic operation with a frame generator and frame -- checker. The GTPs will reset, then attempt to align and transmit data. If channel bonding is -- enabled, bonding should occur after alignment. -- Wire all PLLLKDET signals to the top level as output ports TILE0_PLLLKDET_OUT <= tile0_plllkdet_i; TILE1_PLLLKDET_OUT <= tile1_plllkdet_i; rocketio_wrapper_i : ROCKETIO_WRAPPER generic map ( WRAPPER_SIM_GTPRESET_SPEEDUP => EXAMPLE_SIM_GTPRESET_SPEEDUP, WRAPPER_SIM_PLL_PERDIV2 => EXAMPLE_SIM_PLL_PERDIV2 ) port map ( --_____________________________________________________________________ --_____________________________________________________________________ --TILE0 (X0Y3) ------------------------ Loopback and Powerdown Ports ---------------------- TILE0_LOOPBACK0_IN => tile0_loopback0_i, TILE0_LOOPBACK1_IN => tile0_loopback1_i, TILE0_RXPOWERDOWN0_IN => tile0_rxpowerdown0_i, TILE0_RXPOWERDOWN1_IN => tile0_rxpowerdown1_i, TILE0_TXPOWERDOWN0_IN => tile0_txpowerdown0_i, TILE0_TXPOWERDOWN1_IN => tile0_txpowerdown1_i, ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE0_RXCHARISCOMMA0_OUT => tile0_rxchariscomma0_i, TILE0_RXCHARISCOMMA1_OUT => tile0_rxchariscomma1_i, TILE0_RXCHARISK0_OUT => tile0_rxcharisk0_i, TILE0_RXCHARISK1_OUT => tile0_rxcharisk1_i, TILE0_RXDISPERR0_OUT => tile0_rxdisperr0_i, TILE0_RXDISPERR1_OUT => tile0_rxdisperr1_i, TILE0_RXNOTINTABLE0_OUT => tile0_rxnotintable0_i, TILE0_RXNOTINTABLE1_OUT => tile0_rxnotintable1_i, ------------------- Receive Ports - Channel Bonding Ports ------------------ TILE0_RXCHANBONDSEQ0_OUT => tile0_rxchanbondseq0_i, TILE0_RXCHANBONDSEQ1_OUT => tile0_rxchanbondseq1_i, TILE0_RXENCHANSYNC0_IN => tile0_rxenchansync0_i, TILE0_RXENCHANSYNC1_IN => tile0_rxenchansync1_i, ------------------- Receive Ports - Clock Correction Ports ----------------- TILE0_RXCLKCORCNT0_OUT => tile0_rxclkcorcnt0_i, TILE0_RXCLKCORCNT1_OUT => tile0_rxclkcorcnt1_i, --------------- Receive Ports - Comma Detection and Alignment -------------- TILE0_RXBYTEISALIGNED0_OUT => tile0_rxbyteisaligned0_i, TILE0_RXBYTEISALIGNED1_OUT => tile0_rxbyteisaligned1_i, TILE0_RXBYTEREALIGN0_OUT => tile0_rxbyterealign0_i, TILE0_RXBYTEREALIGN1_OUT => tile0_rxbyterealign1_i, TILE0_RXCOMMADET0_OUT => tile0_rxcommadet0_i, TILE0_RXCOMMADET1_OUT => tile0_rxcommadet1_i, TILE0_RXENMCOMMAALIGN0_IN => tile0_rxenmcommaalign0_i, TILE0_RXENMCOMMAALIGN1_IN => tile0_rxenmcommaalign1_i, TILE0_RXENPCOMMAALIGN0_IN => tile0_rxenpcommaalign0_i, TILE0_RXENPCOMMAALIGN1_IN => tile0_rxenpcommaalign1_i, ------------------- Receive Ports - RX Data Path interface ----------------- TILE0_RXDATA0_OUT => tile0_rxdata0_i, TILE0_RXDATA1_OUT => tile0_rxdata1_i, TILE0_RXRECCLK0_OUT => open , --tile0_rxrecclk0_i, TILE0_RXRECCLK1_OUT => open, --tile0_rxrecclk1_i, TILE0_RXUSRCLK0_IN => tile0_rxusrclk0_i, TILE0_RXUSRCLK1_IN => tile0_rxusrclk1_i, TILE0_RXUSRCLK20_IN => tile0_rxusrclk20_i, TILE0_RXUSRCLK21_IN => tile0_rxusrclk21_i, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE0_RXCDRRESET0_IN => tile0_rxcdrreset0_i, TILE0_RXCDRRESET1_IN => tile0_rxcdrreset1_i, TILE0_RXN0_IN => RXN_IN(0), TILE0_RXN1_IN => RXN_IN(1), TILE0_RXP0_IN => RXP_IN(0), TILE0_RXP1_IN => RXP_IN(1), -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- TILE0_RXBUFSTATUS0_OUT => tile0_rxbufstatus0_i, TILE0_RXBUFSTATUS1_OUT => tile0_rxbufstatus1_i, TILE0_RXCHANISALIGNED0_OUT => tile0_rxchanisaligned0_i, TILE0_RXCHANISALIGNED1_OUT => tile0_rxchanisaligned1_i, TILE0_RXCHANREALIGN0_OUT => tile0_rxchanrealign0_i, TILE0_RXCHANREALIGN1_OUT => tile0_rxchanrealign1_i, --------------- Receive Ports - RX Loss-of-sync State Machine -------------- TILE0_RXLOSSOFSYNC0_OUT => tile0_rxlossofsync0_i, TILE0_RXLOSSOFSYNC1_OUT => tile0_rxlossofsync1_i, --------------------- Shared Ports - Tile and PLL Ports -------------------- TILE0_CLKIN_IN => tile0_refclk_i, TILE0_GTPRESET_IN => GTPRESET_IN, --tile0_gtpreset_i, TILE0_PLLLKDET_OUT => tile0_plllkdet_i, TILE0_REFCLKOUT_OUT => tile0_refclkout_i, TILE0_RESETDONE0_OUT => tile0_resetdone0_i, TILE0_RESETDONE1_OUT => tile0_resetdone1_i, TILE0_TXENPMAPHASEALIGN_IN => txenpmaphasealign_i, TILE0_TXPMASETPHASE_IN => txpmasetphase_i, ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TILE0_TXCHARISK0_IN => tile0_txcharisk0_i, TILE0_TXCHARISK1_IN => tile0_txcharisk1_i, ------------------ Transmit Ports - TX Data Path interface ----------------- TILE0_TXDATA0_IN => tile0_txdata0_i, TILE0_TXDATA1_IN => tile0_txdata1_i, TILE0_TXUSRCLK0_IN => tile0_txusrclk0_i, TILE0_TXUSRCLK1_IN => tile0_txusrclk0_i, TILE0_TXUSRCLK20_IN => tile0_txusrclk20_i, TILE0_TXUSRCLK21_IN => tile0_txusrclk20_i, --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE0_TXN0_OUT => TXN_OUT(0), TILE0_TXN1_OUT => TXN_OUT(1), TILE0_TXP0_OUT => TXP_OUT(0), TILE0_TXP1_OUT => TXP_OUT(1), --_____________________________________________________________________ --_____________________________________________________________________ --TILE1 (X0Y4) ------------------------ Loopback and Powerdown Ports ---------------------- TILE1_LOOPBACK0_IN => tile1_loopback0_i, TILE1_LOOPBACK1_IN => tile1_loopback1_i, TILE1_RXPOWERDOWN0_IN => tile1_rxpowerdown0_i, TILE1_RXPOWERDOWN1_IN => tile1_rxpowerdown1_i, TILE1_TXPOWERDOWN0_IN => tile1_txpowerdown0_i, TILE1_TXPOWERDOWN1_IN => tile1_txpowerdown1_i, ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE1_RXCHARISCOMMA0_OUT => tile1_rxchariscomma0_i, TILE1_RXCHARISCOMMA1_OUT => tile1_rxchariscomma1_i, TILE1_RXCHARISK0_OUT => tile1_rxcharisk0_i, TILE1_RXCHARISK1_OUT => tile1_rxcharisk1_i, TILE1_RXDISPERR0_OUT => tile1_rxdisperr0_i, TILE1_RXDISPERR1_OUT => tile1_rxdisperr1_i, TILE1_RXNOTINTABLE0_OUT => tile1_rxnotintable0_i, TILE1_RXNOTINTABLE1_OUT => tile1_rxnotintable1_i, ------------------- Receive Ports - Channel Bonding Ports ------------------ TILE1_RXCHANBONDSEQ0_OUT => tile1_rxchanbondseq0_i, TILE1_RXCHANBONDSEQ1_OUT => tile1_rxchanbondseq1_i, TILE1_RXENCHANSYNC0_IN => tile1_rxenchansync0_i, TILE1_RXENCHANSYNC1_IN => tile1_rxenchansync1_i, ------------------- Receive Ports - Clock Correction Ports ----------------- TILE1_RXCLKCORCNT0_OUT => tile1_rxclkcorcnt0_i, TILE1_RXCLKCORCNT1_OUT => tile1_rxclkcorcnt1_i, --------------- Receive Ports - Comma Detection and Alignment -------------- TILE1_RXBYTEISALIGNED0_OUT => tile1_rxbyteisaligned0_i, TILE1_RXBYTEISALIGNED1_OUT => tile1_rxbyteisaligned1_i, TILE1_RXBYTEREALIGN0_OUT => tile1_rxbyterealign0_i, TILE1_RXBYTEREALIGN1_OUT => tile1_rxbyterealign1_i, TILE1_RXCOMMADET0_OUT => tile1_rxcommadet0_i, TILE1_RXCOMMADET1_OUT => tile1_rxcommadet1_i, TILE1_RXENMCOMMAALIGN0_IN => tile1_rxenmcommaalign0_i, TILE1_RXENMCOMMAALIGN1_IN => tile1_rxenmcommaalign1_i, TILE1_RXENPCOMMAALIGN0_IN => tile1_rxenpcommaalign0_i, TILE1_RXENPCOMMAALIGN1_IN => tile1_rxenpcommaalign1_i, ------------------- Receive Ports - RX Data Path interface ----------------- TILE1_RXDATA0_OUT => tile1_rxdata0_i, TILE1_RXDATA1_OUT => tile1_rxdata1_i, TILE1_RXRECCLK0_OUT => tile1_rxrecclk0_i, TILE1_RXRECCLK1_OUT => open, --tile1_rxrecclk1_i, TILE1_RXUSRCLK0_IN => tile1_rxusrclk0_i, TILE1_RXUSRCLK1_IN => tile1_rxusrclk1_i, TILE1_RXUSRCLK20_IN => tile1_rxusrclk20_i, TILE1_RXUSRCLK21_IN => tile1_rxusrclk21_i, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE1_RXCDRRESET0_IN => tile1_rxcdrreset0_i, TILE1_RXCDRRESET1_IN => tile1_rxcdrreset1_i, TILE1_RXN0_IN => RXN_IN(2), TILE1_RXN1_IN => RXN_IN(3), TILE1_RXP0_IN => RXP_IN(2), TILE1_RXP1_IN => RXP_IN(3), -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- TILE1_RXBUFSTATUS0_OUT => tile1_rxbufstatus0_i, TILE1_RXBUFSTATUS1_OUT => tile1_rxbufstatus1_i, TILE1_RXCHANISALIGNED0_OUT => tile1_rxchanisaligned0_i, TILE1_RXCHANISALIGNED1_OUT => tile1_rxchanisaligned1_i, TILE1_RXCHANREALIGN0_OUT => tile1_rxchanrealign0_i, TILE1_RXCHANREALIGN1_OUT => tile1_rxchanrealign1_i, --------------- Receive Ports - RX Loss-of-sync State Machine -------------- TILE1_RXLOSSOFSYNC0_OUT => tile1_rxlossofsync0_i, TILE1_RXLOSSOFSYNC1_OUT => tile1_rxlossofsync1_i, --------------------- Shared Ports - Tile and PLL Ports -------------------- TILE1_CLKIN_IN => tile1_refclk_i, TILE1_GTPRESET_IN => GTPRESET_IN, --tile1_gtpreset_i, TILE1_PLLLKDET_OUT => tile1_plllkdet_i, TILE1_REFCLKOUT_OUT => tile1_refclkout_i, TILE1_RESETDONE0_OUT => tile1_resetdone0_i, TILE1_RESETDONE1_OUT => tile1_resetdone1_i, TILE1_TXENPMAPHASEALIGN_IN => txenpmaphasealign_i, TILE1_TXPMASETPHASE_IN => txpmasetphase_i, ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TILE1_TXCHARISK0_IN => tile1_txcharisk0_i, TILE1_TXCHARISK1_IN => tile1_txcharisk1_i, ------------------ Transmit Ports - TX Data Path interface ----------------- TILE1_TXDATA0_IN => tile1_txdata0_i, TILE1_TXDATA1_IN => tile1_txdata1_i, TILE1_TXUSRCLK0_IN => tile1_txusrclk0_i, TILE1_TXUSRCLK1_IN => tile1_txusrclk0_i, TILE1_TXUSRCLK20_IN => tile1_txusrclk20_i, TILE1_TXUSRCLK21_IN => tile1_txusrclk20_i, --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE1_TXN0_OUT => TXN_OUT(2), TILE1_TXN1_OUT => TXN_OUT(3), TILE1_TXP0_OUT => TXP_OUT(2), TILE1_TXP1_OUT => TXP_OUT(3), TXCHARDISPMODE0_1 => txchardispmode1, TXCHARDISPMODE1_2 => txchardispmode2, TXCHARDISPMODE0_3 => txchardispmode3, TXCHARDISPMODE1_4 => txchardispmode4, TXCHARDISPVAL0_1 => txchardispval1, TXCHARDISPVAL1_2 => txchardispval2, TXCHARDISPVAL0_3 => txchardispval3, TXCHARDISPVAL1_4 => txchardispval4, RXRESET0_IN1 => RXRESET0_IN1, RXRESET0_IN2 => RXRESET0_IN2, RXRESET0_IN3 => RXRESET0_IN3, RXRESET0_IN4 => RXRESET0_IN4, TXKERR0_1 => TXKERR0_1, TXKERR1_2 => TXKERR1_2, TXKERR0_3 => TXKERR0_3, TXKERR1_4 => TXKERR1_4, TXRUNDISP0_1 => TXRUNDISP0_1, TXRUNDISP1_2 => TXRUNDISP1_2, TXRUNDISP0_3 => TXRUNDISP0_3, TXRUNDISP1_4 => TXRUNDISP1_4, TXBUFSTATUS0_1 => TXBUFSTATUS0_1, TXBUFSTATUS1_2 => TXBUFSTATUS1_2, TXBUFSTATUS0_3 => TXBUFSTATUS0_3, TXBUFSTATUS1_4 => TXBUFSTATUS1_4, RXSTATUS0_1 => RXSTATUS0_1, RXSTATUS1_2 => RXSTATUS1_2, RXSTATUS0_3 => RXSTATUS0_3, RXSTATUS1_4 => RXSTATUS1_4, PHYSTATUS0_1 => PHYSTATUS0_1, PHYSTATUS1_2 => PHYSTATUS1_2, PHYSTATUS0_3 => PHYSTATUS0_3, PHYSTATUS1_4 => PHYSTATUS1_4, rxelecidle0_1 => rxelecidle0_1, rxelecidle1_2 => rxelecidle1_2, rxelecidle0_3 => rxelecidle0_3, rxelecidle1_4 => rxelecidle1_4, RXPRBSERR0_1 => RXPRBSERR0_1, RXPRBSERR1_2 => RXPRBSERR1_2, RXPRBSERR0_3 => RXPRBSERR0_3, RXPRBSERR1_4 => RXPRBSERR1_4, RXRUNDISP0_1 => RXRUNDISP0_1, RXRUNDISP1_2 => RXRUNDISP1_2, RXRUNDISP0_3 => RXRUNDISP0_3, RXRUNDISP1_4 => RXRUNDISP1_4 ); ------------------------------ TXSYNC module ------------------------------ -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It -- waits for the user clocks to be stable, then drives the phase align signals on each -- GTP. When phase synchronization is complete, it asserts SYNC_DONE -- Include the TX_SYNC module in your own design to perform phase synchronization if -- your protocol bypasses the TX Buffers reset_txsync_c <= not tile0_resetdone0_r2; tile0_txsync_i : TX_SYNC port map ( TXENPMAPHASEALIGN => txenpmaphasealign_i, TXPMASETPHASE => txpmasetphase_i, SYNC_DONE => tx_sync_done_i, USER_CLK => tile0_txusrclk20_i, RESET => reset_txsync_c ); -------------------------- User Module Resets ----------------------------- -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules -- are held in reset till the RESETDONE goes high. -- The RESETDONE is registered a couple of times on USRCLK2 and connected -- to the reset of the modules process( tile0_rxusrclk20_i,tile0_resetdone0_i) begin if(tile0_resetdone0_i = '0') then tile0_resetdone0_r <= '0' after DLY; tile0_resetdone0_r2 <= '0' after DLY; elsif(tile0_rxusrclk20_i'event and tile0_rxusrclk20_i = '1') then tile0_resetdone0_r <= tile0_resetdone0_i after DLY; tile0_resetdone0_r2 <= tile0_resetdone0_r after DLY; end if; end process; process( tile0_rxusrclk21_i,tile0_resetdone1_i) begin if(tile0_resetdone1_i = '0') then tile0_resetdone1_r <= '0' after DLY; tile0_resetdone1_r2 <= '0' after DLY; elsif(tile0_rxusrclk21_i'event and tile0_rxusrclk21_i = '1') then tile0_resetdone1_r <= tile0_resetdone1_i after DLY; tile0_resetdone1_r2 <= tile0_resetdone1_r after DLY; end if; end process; process( tile1_rxusrclk20_i,tile1_resetdone0_i) begin if(tile1_resetdone0_i = '0') then tile1_resetdone0_r <= '0' after DLY; tile1_resetdone0_r2 <= '0' after DLY; elsif(tile1_rxusrclk20_i'event and tile1_rxusrclk20_i = '1') then tile1_resetdone0_r <= tile1_resetdone0_i after DLY; tile1_resetdone0_r2 <= tile1_resetdone0_r after DLY; end if; end process; process( tile1_rxusrclk21_i,tile1_resetdone1_i) begin if(tile1_resetdone1_i = '0') then tile1_resetdone1_r <= '0' after DLY; tile1_resetdone1_r2 <= '0' after DLY; elsif(tile1_rxusrclk21_i'event and tile1_rxusrclk21_i = '1') then tile1_resetdone1_r <= tile1_resetdone1_i after DLY; tile1_resetdone1_r2 <= tile1_resetdone1_r after DLY; end if; end process; ------------------------------ Frame Generators --------------------------- -- The example design uses Block RAM based frame generators to provide test -- data to the GTPs for transmission. By default the frame generators are -- loaded with an incrementing data sequence that includes commas/alignment -- characters for alignment. If your protocol uses channel bonding, the -- frame generator will also be preloaded with a channel bonding sequence. -- You can modify the data transmitted by changing the INIT values of the frame -- generator in this file. Pay careful attention to bit order and the spacing -- of your control and alignment characters. tile0_frame_gen0 : FRAME_GEN generic map ( WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- User Interface TX_DATA(31 downto 16) => tile0_txdata0_float_i, TX_DATA(15 downto 0) => tile0_txdata0_ii, TX_CHARISK(3 downto 2) => tile0_txcharisk0_float_i, TX_CHARISK(1 downto 0) => tile0_txcharisk0_ii, -- System Interface USER_CLK => tile0_txusrclk20_i, SYSTEM_RESET => tx_system_reset_c ); tile0_frame_gen1 : FRAME_GEN generic map ( WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- User Interface TX_DATA(31 downto 16) => tile0_txdata1_float_i, TX_DATA(15 downto 0) => tile0_txdata1_ii, TX_CHARISK(3 downto 2) => tile0_txcharisk1_float_i, TX_CHARISK(1 downto 0) => tile0_txcharisk1_ii, -- System Interface USER_CLK => tile0_txusrclk20_i, SYSTEM_RESET => tx_system_reset_c ); tile1_frame_gen0 : FRAME_GEN generic map ( WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- User Interface TX_DATA(31 downto 16) => tile1_txdata0_float_i, TX_DATA(15 downto 0) => tile1_txdata0_ii, TX_CHARISK(3 downto 2) => tile1_txcharisk0_float_i, TX_CHARISK(1 downto 0) => tile1_txcharisk0_ii, -- System Interface USER_CLK => tile1_txusrclk20_i, SYSTEM_RESET => tx_system_reset_c ); tile1_frame_gen1 : FRAME_GEN generic map ( WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- User Interface TX_DATA(31 downto 16) => tile1_txdata1_float_i, TX_DATA(15 downto 0) => tile1_txdata1_ii, TX_CHARISK(3 downto 2) => tile1_txcharisk1_float_i, TX_CHARISK(1 downto 0) => tile1_txcharisk1_ii, -- System Interface USER_CLK => tile1_txusrclk20_i, SYSTEM_RESET => tx_system_reset_c ); ---------------------------------- Frame Checkers ------------------------- -- The example design uses Block RAM based frame checkers to verify incoming -- data. By default the frame generators are loaded with a data sequence that -- matches the outgoing sequence of the frame generators for the TX ports. -- You can modify the expected data sequence by changing the INIT values of the frame -- checkers in this file. Pay careful attention to bit order and the spacing -- of your control and alignment characters. -- When the frame checker receives data, it attempts to synchronise to the -- incoming pattern by looking for the first sequence in the pattern. Once it -- finds the first sequence, it increments through the sequence, and indicates an -- error whenever the next value received does not match the expected value. tile0_frame_check0_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else tile0_matchn0_i; -- tile0_frame_check0 is always connected to the lane with the start of char -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off tile0_inc_in0_i <= '0'; tile0_frame_check0 : FRAME_CHECK generic map ( RX_DATA_WIDTH => 16, USE_COMMA => 1, WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, CONFIG_INDEPENDENT_LANES => 1, START_OF_PACKET_CHAR => x"00bc", MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- MGT Interface RX_DATA => tile0_rxdata0_i, RX_ENMCOMMA_ALIGN => open, --tile0_rxenmcommaalign0_i, RX_ENPCOMMA_ALIGN => open, --tile0_rxenpcommaalign0_i, RX_ENCHAN_SYNC => tile0_rxenchansync0_i, -- Control Interface INC_IN => tile0_inc_in0_i, INC_OUT => tile0_inc_out0_i, PATTERN_MATCH_N => tile0_matchn0_i, RESET_ON_ERROR => tile0_frame_check0_reset_i, -- System Interface USER_CLK => tile0_rxusrclk20_i, SYSTEM_RESET => tile0_rx_system_reset0_c, ERROR_COUNT => tile0_error_count0_i ); process(tile0_rxusrclk20_i) begin if tile0_rxusrclk20_i'event and tile0_rxusrclk20_i = '1' then -- if tile0_rx_system_reset0_c = '1' then -- tile0_rxenmcommaalign0_i <= '0'; -- tile0_rxenpcommaalign0_i <= '0'; -- else tile0_rxenmcommaalign0_i <= '1'; tile0_rxenpcommaalign0_i <= '1'; -- end if; end if; end process; tile0_frame_check1_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else tile0_matchn1_i; -- tile0_frame_check0 is always connected to the lane with the start of char -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off tile0_inc_in1_i <= '0'; tile0_frame_check1 : FRAME_CHECK generic map ( RX_DATA_WIDTH => 16, USE_COMMA => 1, WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, CONFIG_INDEPENDENT_LANES => 1, START_OF_PACKET_CHAR => x"00bc", MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- MGT Interface RX_DATA => tile0_rxdata1_i, RX_ENMCOMMA_ALIGN => open, --tile0_rxenmcommaalign1_i, RX_ENPCOMMA_ALIGN => open, --tile0_rxenpcommaalign1_i, RX_ENCHAN_SYNC => tile0_rxenchansync1_i, -- Control Interface INC_IN => tile0_inc_in1_i, INC_OUT => tile0_inc_out1_i, PATTERN_MATCH_N => tile0_matchn1_i, RESET_ON_ERROR => tile0_frame_check1_reset_i, -- System Interface USER_CLK => tile0_rxusrclk21_i, SYSTEM_RESET => tile0_rx_system_reset1_c, ERROR_COUNT => tile0_error_count1_i ); process(tile0_rxusrclk21_i) begin if tile0_rxusrclk21_i'event and tile0_rxusrclk21_i = '1' then -- if tile0_rx_system_reset1_c = '1' then -- tile0_rxenmcommaalign1_i <= '0'; -- tile0_rxenpcommaalign1_i <= '0'; -- else tile0_rxenmcommaalign1_i <= '1'; tile0_rxenpcommaalign1_i <= '1'; -- end if; end if; end process; tile1_frame_check0_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else tile1_matchn0_i; -- in the "independent lanes" configuration, each of the lanes looks for the unique start char and -- in this case, the INC_IN port is tied off. -- Else, the data checking is triggered by the "master" lane tile1_inc_in0_i <= tile0_inc_out0_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else '0'; tile1_frame_check0 : FRAME_CHECK generic map ( RX_DATA_WIDTH => 16, USE_COMMA => 1, WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, CONFIG_INDEPENDENT_LANES => EXAMPLE_CONFIG_INDEPENDENT_LANES, START_OF_PACKET_CHAR => x"00bc", MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- MGT Interface RX_DATA => tile1_rxdata0_i, RX_ENMCOMMA_ALIGN => open, --tile1_rxenmcommaalign0_i, RX_ENPCOMMA_ALIGN => open, --tile1_rxenpcommaalign0_i, RX_ENCHAN_SYNC => tile1_rxenchansync0_i, -- Control Interface INC_IN => tile1_inc_in0_i, INC_OUT => tile1_inc_out0_i, PATTERN_MATCH_N => tile1_matchn0_i, RESET_ON_ERROR => tile1_frame_check0_reset_i, -- System Interface USER_CLK => tile1_rxusrclk20_i, SYSTEM_RESET => tile1_rx_system_reset0_c, ERROR_COUNT => tile1_error_count0_i ); process(tile1_rxusrclk20_i) begin if tile1_rxusrclk21_i'event and tile1_rxusrclk21_i = '1' then -- if tile1_rx_system_reset0_c = '1' then -- tile1_rxenmcommaalign0_i <= '0'; -- tile1_rxenpcommaalign0_i <= '0'; -- else tile1_rxenmcommaalign0_i <= '1'; tile1_rxenpcommaalign0_i <= '1'; -- end if; end if; end process; tile1_frame_check1_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else tile1_matchn1_i; -- in the "independent lanes" configuration, each of the lanes looks for the unique start char and -- in this case, the INC_IN port is tied off. -- Else, the data checking is triggered by the "master" lane tile1_inc_in1_i <= tile0_inc_out1_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else '0'; tile1_frame_check1 : FRAME_CHECK generic map ( RX_DATA_WIDTH => 16, USE_COMMA => 1, WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM, CONFIG_INDEPENDENT_LANES => EXAMPLE_CONFIG_INDEPENDENT_LANES, START_OF_PACKET_CHAR => x"00bc", MEM_00 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_01 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_02 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_03 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_04 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_05 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_06 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_07 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_08 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_09 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_0A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_0B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_0C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_0D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_0E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_0F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_10 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_11 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_12 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_13 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_14 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_15 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_16 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_17 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_18 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_19 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_1A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_1B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_1C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_1D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_1E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_1F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_20 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_21 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_22 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_23 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_24 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_25 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_26 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_27 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_28 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_29 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_2A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_2B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_2C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_2D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_2E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_2F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_30 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_31 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_32 => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_33 => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_34 => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_35 => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_36 => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_37 => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEM_38 => x"00000e0d00000c0b00000a0900000807000006050000040300000201000000bc", MEM_39 => x"00001e1d00001c1b00001a19000018170000161500001413000012110000100f", MEM_3A => x"00002e2d00002c2b00002a29000028270000262500002423000022210000201f", MEM_3B => x"00003e3d00003c3b00003a39000038370000363500003433000032310000302f", MEM_3C => x"00004e4d00004c4b00004a49000048470000464500004443000042410000403f", MEM_3D => x"00005e5d00005c5b00005a59000058570000565500005453000052510000504f", MEM_3E => x"00006e6d00006c6b00006a69000068670000666500006463000062610000605f", MEM_3F => x"0000007d00007c7b00007a79000078770000767500007473000072710000706f", MEMP_00 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_01 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_02 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_03 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_04 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_05 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_06 => x"2000000000000000000000000000000000000000000000000000000000000001", MEMP_07 => x"2000000000000000000000000000000000000000000000000000000000000001" ) port map ( -- MGT Interface RX_DATA => tile1_rxdata1_i, RX_ENMCOMMA_ALIGN => open, --tile1_rxenmcommaalign1_i, RX_ENPCOMMA_ALIGN => open, --tile1_rxenpcommaalign1_i, RX_ENCHAN_SYNC => tile1_rxenchansync1_i, -- Control Interface INC_IN => tile1_inc_in1_i, INC_OUT => tile1_inc_out1_i, PATTERN_MATCH_N => tile1_matchn1_i, RESET_ON_ERROR => tile1_frame_check1_reset_i, -- System Interface USER_CLK => tile1_rxusrclk21_i, SYSTEM_RESET => tile1_rx_system_reset1_c, ERROR_COUNT => tile1_error_count1_i ); process(tile1_rxusrclk21_i) begin if tile1_rxusrclk21_i'event and tile1_rxusrclk21_i = '1' then -- if tile1_rx_system_reset1_c = '1' then -- tile1_rxenmcommaalign1_i <= '0'; -- tile1_rxenpcommaalign1_i <= '0'; -- else tile1_rxenmcommaalign1_i <= '1'; tile1_rxenpcommaalign1_i <= '1'; -- end if; end if; end process; -- To support channel bonding, the pattern_match_n ports of each frame_check module -- are ORed together. Each frame checker has a parameter called CONFIG_INDEPENDANT_LANES -- which, when set to 0, causes the frame generators to use the ORed match signals. This -- causes the lanes to synchronize and check a combined sequence across multiple blocks. If -- CONFIG_INDEPENDANT_LANES is 1, each the lane will self-syncronize and check for errors -- seperately from the other frame checkers. reset_on_data_error_i <= tile0_matchn0_i or tile1_matchn1_i ; ----------------------------- Chipscope Connections ----------------------- -- When the example design is run in hardware, it uses chipscope to allow the -- example design and GTP wrapper to be controlled and monitored. The -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation. -- --chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate -- -- -- -- Shared VIO for all tiles -- shared_vio_i : shared_vio -- port map -- ( -- control => shared_vio_control_i, -- async_in => shared_vio_in_i, -- async_out => shared_vio_out_i -- ); -- -- -- -- ICON for all VIOs -- i_icon : icon -- port map -- ( -- control0 => shared_vio_control_i, -- control1 => tx_data_vio_control0_i, -- control2 => rx_data_vio_control0_i, -- control3 => ila_control0_i, -- control4 => tx_data_vio_control1_i, -- control5 => rx_data_vio_control1_i, -- control6 => ila_control1_i -- ); -- -- -- TX VIO -- tx_data_vio0_i : shared_vio -- port map -- ( -- control => tx_data_vio_control0_i, -- async_in => tx_data_vio_in0_i, -- async_out => tx_data_vio_out0_i -- ); -- -- -- RX VIO -- rx_data_vio0_i : shared_vio -- port map -- ( -- control => rx_data_vio_control0_i, -- async_in => rx_data_vio_in0_i, -- async_out => rx_data_vio_out0_i -- ); -- -- -- RX ILA -- ila0_i : ila -- port map -- ( -- control => ila_control0_i, -- clk => ila_clk0_i, -- trig0 => ila_in0_r -- ); -- -- -- -- -- -- The RX ILA must use the same clock as the selected transceiver -- ila_clk0_bufg_i : BUFG -- port map -- ( -- I => ila_clk_mux_out0_i, -- O => ila_clk0_i -- ); -- -- ila_clk_mux_out0_i <= tile0_rxusrclk20_i when (mux_sel_i = '0') -- else tile1_rxusrclk20_i; -- -- -- -- -- Register the ILA input to add slack to the timing. Don't change mux_sel while -- -- triggering for data -- process( ila_clk0_i ) -- begin -- if( ila_clk0_i'event and ila_clk0_i = '1' ) then -- ila_in0_r <= ila_in0_i; -- end if; -- end process; -- -- -- TX VIO -- tx_data_vio1_i : shared_vio -- port map -- ( -- control => tx_data_vio_control1_i, -- async_in => tx_data_vio_in1_i, -- async_out => tx_data_vio_out1_i -- ); -- -- -- RX VIO -- rx_data_vio1_i : shared_vio -- port map -- ( -- control => rx_data_vio_control1_i, -- async_in => rx_data_vio_in1_i, -- async_out => rx_data_vio_out1_i -- ); -- -- -- RX ILA -- ila1_i : ila -- port map -- ( -- control => ila_control1_i, -- clk => ila_clk1_i, -- trig0 => ila_in1_r -- ); -- -- -- -- -- -- The RX ILA must use the same clock as the selected transceiver -- ila_clk1_bufg_i : BUFG -- port map -- ( -- I => ila_clk_mux_out1_i, -- O => ila_clk1_i -- ); -- -- ila_clk_mux_out1_i <= tile0_rxusrclk21_i when (mux_sel_i = '0') -- else tile1_rxusrclk21_i; -- -- -- -- -- Register the ILA input to add slack to the timing. Don't change mux_sel while -- -- triggering for data -- process( ila_clk1_i ) -- begin -- if( ila_clk1_i'event and ila_clk1_i = '1' ) then -- ila_in1_r <= ila_in1_i; -- end if; -- end process; -- -- -- -- Connect resets for frame generators -- tx_system_reset_c <= not tx_sync_done_i or user_tx_reset_i; -- tile0_rx_system_reset0_c <= not tile0_resetdone0_r2 or user_rx_reset_i; -- tile0_rx_system_reset1_c <= not tile0_resetdone1_r2 or user_rx_reset_i; -- tile1_rx_system_reset0_c <= not tile1_resetdone0_r2 or user_rx_reset_i; -- tile1_rx_system_reset1_c <= not tile1_resetdone1_r2 or user_rx_reset_i; -- -- -- tile0_gtpreset_i <= gtpreset_i; -- tile1_gtpreset_i <= gtpreset_i; -- -- -- -- Shared VIO Outputs -- gtpreset_i <= shared_vio_out_i(31); -- user_tx_reset_i <= shared_vio_out_i(30); -- user_rx_reset_i <= shared_vio_out_i(29); -- mux_sel_i <= shared_vio_out_i(28); -- -- -- Shared VIO Inputs -- shared_vio_in_i(31) <= tile0_plllkdet_i; -- shared_vio_in_i(30) <= tile1_plllkdet_i; -- shared_vio_in_i(29 downto 0) <= "000000000000000000000000000000"; -- -- -- Chipscope connections for GTP0 on Tile 0 -- tile0_tx_data_vio_in0_i(31 downto 0) <= "00000000000000000000000000000000"; -- tile0_loopback0_i <= tx_data_vio_out0_i(31 downto 29); -- tile0_txpowerdown0_i <= tx_data_vio_out0_i(28 downto 27); -- tile0_rx_data_vio_in0_i(31) <= tile0_resetdone0_i; -- tile0_rx_data_vio_in0_i(30 downto 0) <= "0000000000000000000000000000000"; -- tile0_rxpowerdown0_i <= rx_data_vio_out0_i(31 downto 30); -- tile0_rxcdrreset0_i <= rx_data_vio_out0_i(29); -- tile0_ila_in0_i(63 downto 62) <= tile0_rxchariscomma0_i; -- tile0_ila_in0_i(61 downto 60) <= tile0_rxcharisk0_i; -- tile0_ila_in0_i(59 downto 58) <= tile0_rxdisperr0_i; -- tile0_ila_in0_i(57 downto 56) <= tile0_rxnotintable0_i; -- tile0_ila_in0_i(55) <= tile0_rxchanbondseq0_i; -- tile0_ila_in0_i(54 downto 52) <= tile0_rxclkcorcnt0_i; -- tile0_ila_in0_i(51) <= tile0_rxbyteisaligned0_i; -- tile0_ila_in0_i(50) <= tile0_rxbyterealign0_i; -- tile0_ila_in0_i(49) <= tile0_rxcommadet0_i; -- tile0_ila_in0_i(48 downto 33) <= tile0_rxdata0_i; -- tile0_ila_in0_i(32 downto 30) <= tile0_rxbufstatus0_i; -- tile0_ila_in0_i(29) <= tile0_rxchanisaligned0_i; -- tile0_ila_in0_i(28) <= tile0_rxchanrealign0_i; -- tile0_ila_in0_i(27 downto 26) <= tile0_rxlossofsync0_i; -- tile0_ila_in0_i(25 downto 18) <= tile0_error_count0_i; -- tile0_ila_in0_i(17 downto 0) <= "000000000000000000"; -- -- -- Chipscope connections for GTP1 on Tile 0 -- tile0_tx_data_vio_in1_i(31 downto 0) <= "00000000000000000000000000000000"; -- tile0_loopback1_i <= tx_data_vio_out1_i(31 downto 29); -- tile0_txpowerdown1_i <= tx_data_vio_out1_i(28 downto 27); -- tile0_rx_data_vio_in1_i(31) <= tile0_resetdone1_i; -- tile0_rx_data_vio_in1_i(30 downto 0) <= "0000000000000000000000000000000"; -- tile0_rxpowerdown1_i <= rx_data_vio_out1_i(31 downto 30); -- tile0_rxcdrreset1_i <= rx_data_vio_out1_i(29); -- tile0_ila_in1_i(63 downto 62) <= tile0_rxchariscomma1_i; -- tile0_ila_in1_i(61 downto 60) <= tile0_rxcharisk1_i; -- tile0_ila_in1_i(59 downto 58) <= tile0_rxdisperr1_i; -- tile0_ila_in1_i(57 downto 56) <= tile0_rxnotintable1_i; -- tile0_ila_in1_i(55) <= tile0_rxchanbondseq1_i; -- tile0_ila_in1_i(54 downto 52) <= tile0_rxclkcorcnt1_i; -- tile0_ila_in1_i(51) <= tile0_rxbyteisaligned1_i; -- tile0_ila_in1_i(50) <= tile0_rxbyterealign1_i; -- tile0_ila_in1_i(49) <= tile0_rxcommadet1_i; -- tile0_ila_in1_i(48 downto 33) <= tile0_rxdata1_i; -- tile0_ila_in1_i(32 downto 30) <= tile0_rxbufstatus1_i; -- tile0_ila_in1_i(29) <= tile0_rxchanisaligned1_i; -- tile0_ila_in1_i(28) <= tile0_rxchanrealign1_i; -- tile0_ila_in1_i(27 downto 26) <= tile0_rxlossofsync1_i; -- tile0_ila_in1_i(25 downto 18) <= tile0_error_count1_i; -- tile0_ila_in1_i(17 downto 0) <= "000000000000000000"; -- -- -- Chipscope connections for GTP0 on Tile 1 -- tile1_tx_data_vio_in0_i(31 downto 0) <= "00000000000000000000000000000000"; -- tile1_loopback0_i <= tx_data_vio_out0_i(31 downto 29); -- tile1_txpowerdown0_i <= tx_data_vio_out0_i(28 downto 27); -- tile1_rx_data_vio_in0_i(31) <= tile1_resetdone0_i; -- tile1_rx_data_vio_in0_i(30 downto 0) <= "0000000000000000000000000000000"; -- tile1_rxpowerdown0_i <= rx_data_vio_out0_i(31 downto 30); -- tile1_rxcdrreset0_i <= rx_data_vio_out0_i(29); -- tile1_ila_in0_i(63 downto 62) <= tile1_rxchariscomma0_i; -- tile1_ila_in0_i(61 downto 60) <= tile1_rxcharisk0_i; -- tile1_ila_in0_i(59 downto 58) <= tile1_rxdisperr0_i; -- tile1_ila_in0_i(57 downto 56) <= tile1_rxnotintable0_i; -- tile1_ila_in0_i(55) <= tile1_rxchanbondseq0_i; -- tile1_ila_in0_i(54 downto 52) <= tile1_rxclkcorcnt0_i; -- tile1_ila_in0_i(51) <= tile1_rxbyteisaligned0_i; -- tile1_ila_in0_i(50) <= tile1_rxbyterealign0_i; -- tile1_ila_in0_i(49) <= tile1_rxcommadet0_i; -- tile1_ila_in0_i(48 downto 33) <= tile1_rxdata0_i; -- tile1_ila_in0_i(32 downto 30) <= tile1_rxbufstatus0_i; -- tile1_ila_in0_i(29) <= tile1_rxchanisaligned0_i; -- tile1_ila_in0_i(28) <= tile1_rxchanrealign0_i; -- tile1_ila_in0_i(27 downto 26) <= tile1_rxlossofsync0_i; -- tile1_ila_in0_i(25 downto 18) <= tile1_error_count0_i; -- tile1_ila_in0_i(17 downto 0) <= "000000000000000000"; -- -- -- Chipscope connections for GTP1 on Tile 1 -- tile1_tx_data_vio_in1_i(31 downto 0) <= "00000000000000000000000000000000"; -- tile1_loopback1_i <= tx_data_vio_out1_i(31 downto 29); -- tile1_txpowerdown1_i <= tx_data_vio_out1_i(28 downto 27); -- tile1_rx_data_vio_in1_i(31) <= tile1_resetdone1_i; -- tile1_rx_data_vio_in1_i(30 downto 0) <= "0000000000000000000000000000000"; -- tile1_rxpowerdown1_i <= rx_data_vio_out1_i(31 downto 30); -- tile1_rxcdrreset1_i <= rx_data_vio_out1_i(29); -- tile1_ila_in1_i(63 downto 62) <= tile1_rxchariscomma1_i; -- tile1_ila_in1_i(61 downto 60) <= tile1_rxcharisk1_i; -- tile1_ila_in1_i(59 downto 58) <= tile1_rxdisperr1_i; -- tile1_ila_in1_i(57 downto 56) <= tile1_rxnotintable1_i; -- tile1_ila_in1_i(55) <= tile1_rxchanbondseq1_i; -- tile1_ila_in1_i(54 downto 52) <= tile1_rxclkcorcnt1_i; -- tile1_ila_in1_i(51) <= tile1_rxbyteisaligned1_i; -- tile1_ila_in1_i(50) <= tile1_rxbyterealign1_i; -- tile1_ila_in1_i(49) <= tile1_rxcommadet1_i; -- tile1_ila_in1_i(48 downto 33) <= tile1_rxdata1_i; -- tile1_ila_in1_i(32 downto 30) <= tile1_rxbufstatus1_i; -- tile1_ila_in1_i(29) <= tile1_rxchanisaligned1_i; -- tile1_ila_in1_i(28) <= tile1_rxchanrealign1_i; -- tile1_ila_in1_i(27 downto 26) <= tile1_rxlossofsync1_i; -- tile1_ila_in1_i(25 downto 18) <= tile1_error_count1_i; -- tile1_ila_in1_i(17 downto 0) <= "000000000000000000"; -- -- -- --Mux inputs to Chipscope modules based on mux_sel_i -- tx_data_vio_in0_i <= tile0_tx_data_vio_in0_i when (mux_sel_i = '0') -- else tile1_tx_data_vio_in0_i; -- -- -- rx_data_vio_in0_i <= tile0_rx_data_vio_in0_i when (mux_sel_i = '0') -- else tile1_rx_data_vio_in0_i; -- -- -- ila_in0_i <= tile0_ila_in0_i when (mux_sel_i = '0') -- else tile1_ila_in0_i; -- -- -- tx_data_vio_in1_i <= tile0_tx_data_vio_in1_i when (mux_sel_i = '0') -- else tile1_tx_data_vio_in1_i; -- -- -- rx_data_vio_in1_i <= tile0_rx_data_vio_in1_i when (mux_sel_i = '0') -- else tile1_rx_data_vio_in1_i; -- -- -- ila_in1_i <= tile0_ila_in1_i when (mux_sel_i = '0') -- else tile1_ila_in1_i; -- -- -- -- -- --end generate chipscope; -- no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate -- If Chipscope is not being used, drive GTP reset signal -- from the top level ports tile0_gtpreset_i <= GTPRESET_IN; tile1_gtpreset_i <= GTPRESET_IN; GTP_SYSTEM_RESET <= tx_system_reset_c; -- assign resets for frame_gen and frame_check modules tx_system_reset_c <= not tx_sync_done_i; tile0_rx_system_reset0_c <= not tile0_resetdone0_r2; tile0_rx_system_reset1_c <= not tile0_resetdone1_r2; tile1_rx_system_reset0_c <= not tile1_resetdone0_r2; tile1_rx_system_reset1_c <= not tile1_resetdone1_r2; gtpreset_i <= tied_to_ground_i; user_tx_reset_i <= tied_to_ground_i; user_rx_reset_i <= tied_to_ground_i; mux_sel_i <= tied_to_ground_i; tile0_loopback0_i <= tied_to_ground_vec_i(2 downto 0); tile0_txpowerdown0_i <= tied_to_ground_vec_i(1 downto 0); tile0_rxpowerdown0_i <= tied_to_ground_vec_i(1 downto 0); tile0_rxcdrreset0_i <= tied_to_ground_i; tile0_loopback1_i <= tied_to_ground_vec_i(2 downto 0); tile0_txpowerdown1_i <= tied_to_ground_vec_i(1 downto 0); tile0_rxpowerdown1_i <= tied_to_ground_vec_i(1 downto 0); tile0_rxcdrreset1_i <= tied_to_ground_i; tile1_loopback0_i <= tied_to_ground_vec_i(2 downto 0); tile1_txpowerdown0_i <= tied_to_ground_vec_i(1 downto 0); tile1_rxpowerdown0_i <= tied_to_ground_vec_i(1 downto 0); tile1_rxcdrreset0_i <= tied_to_ground_i; tile1_loopback1_i <= tied_to_ground_vec_i(2 downto 0); tile1_txpowerdown1_i <= tied_to_ground_vec_i(1 downto 0); tile1_rxpowerdown1_i <= tied_to_ground_vec_i(1 downto 0); tile1_rxcdrreset1_i <= tied_to_ground_i; end generate no_chipscope; -- pack_inst : trans_test2 -- port map ( clka => tile0_txusrclk20_i, -- clkb => tile0_txusrclk20_i, -- clkc => tile1_txusrclk20_i, -- rst => GTPRESET_IN, --tx_system_reset_c, -- dout1 => open, --tile0_txdata0_i, -- dout2 => open, --tile0_txdata1_i, -- dout3 => open, --tile1_txdata0_i, -- char1 => open, --tile0_txcharisk0_i, -- char2 => open, --tile0_txcharisk1_i, -- char3 => open, --tile1_txcharisk0_i, -- fout => open, -- valid_regceb => valid_regceb, -- valid_data => valid_data, -- valid_clk => valid_clk, -- wr_en1_out => wr_en1_out, -- wr_en2_out => wr_en2_out --); ----wr_en2_out <= tile0_txcharisk0_i(0); --tile1_txdata1_i <= tile1_txdata0_i; --tile1_txcharisk1_i <= tile1_txcharisk0_i; --tile0_txdata0_i <= X"4141"; --tile0_txdata1_i <= X"E1E1"; --tile1_txdata0_i <= X"F2F2"; --tile0_txcharisk0_i <= "01"; --process(tile0_txusrclk20_i) --begin -- if tile0_txusrclk20_i'event and tile0_txusrclk20_i = '1' then -- cnt <= cnt + '1'; -- if cnt < 1023 then -- tile0_txdata0_i <= X"4141"; -- tile0_txdata1_i <= X"E1E1"; -- tile1_txdata0_i <= X"F2F2"; -- tile0_txcharisk0_i <= "00"; -- tile0_txcharisk1_i <= "00"; -- tile1_txcharisk0_i <= "00"; -- -- elsif cnt = 1023 then -- tile0_txdata0_i <= X"00BC"; -- tile0_txdata1_i <= X"00BC"; -- tile1_txdata0_i <= X"00BC"; -- tile0_txcharisk0_i <= "01"; -- tile0_txcharisk1_i <= "01"; -- tile1_txcharisk0_i <= "01"; -- end if; -- end if; --end process; ----------------------------------------------------------------------------------------- ----Generation of RESET for individual tiles transmiter section to TX PACKETIZATION -- vani 31/3/09 process(tile0_txusrclk20_i) begin if refclkout_pll2_locked_i = '0' then TILE0_TMP_RST <= '0'; elsif tile0_txusrclk20_i'event and tile0_txusrclk20_i = '1' then if TILE0_TMP_RST = '0' then tile0_cnt <= tile0_cnt + '1'; if tile0_cnt < 7 then TILE0TX_RST <= '1'; elsif tile0_cnt = 7 then TILE0TX_RST <= '0'; tile0_cnt <= (others => '0'); TILE0_TMP_RST <= '1'; end if; end if; end if; end process; process(tile1_txusrclk20_i) begin if refclkout_pll5_locked_i = '0' then TILE1_TMP_RST <= '0'; elsif tile1_txusrclk20_i'event and tile1_txusrclk20_i = '1' then if TILE1_TMP_RST = '0' then tile1_cnt <= tile1_cnt + '1'; if tile1_cnt < 7 then TILE1TX_RST <= '1'; elsif tile1_cnt = 7 then TILE1TX_RST <= '0'; tile1_cnt <= (others => '0'); TILE1_TMP_RST <= '1'; end if; end if; end if; end process; --process(tile0_txusrclk20_i) --begin -- if tile0_txusrclk20_i'event and tile0_txusrclk20_i = '1' then refclkout_pll2_locked_out <= refclkout_pll2_locked_i; -- end if; --end process; --process(tile1_txusrclk20_i) --begin --if tile1_txusrclk20_i'event and tile1_txusrclk20_i = '1' then refclkout_pll5_locked_out <= refclkout_pll5_locked_i; --end if; --end process; ----------------------------------------------------------------------------------------------- ----Generation of RESET for individual tiles receiver section to RX PACKETIZATION -- vani 31/3/09 process(tile0_rxusrclk20_i) begin if rxrecclk_dcm0_locked_i = '0' then TILE0RX_TMP_RST0 <= '0'; elsif tile0_rxusrclk20_i'event and tile0_rxusrclk20_i = '1' then if TILE0RX_TMP_RST0 = '0' then tile0_cnt0 <= tile0_cnt0 + '1'; if tile0_cnt0 < 7 then TILE0RX_RST0 <= '1'; elsif tile0_cnt0 = 7 then TILE0RX_RST0 <= '0'; tile0_cnt0 <= (others => '0'); TILE0RX_TMP_RST0 <= '1'; end if; end if; end if; end process; --process(tile0_rxusrclk20_i) --begin --if tile0_rxusrclk20_i'event and tile0_rxusrclk20_i = '1' then rxrecclk_dcm0_locked_out <= rxrecclk_dcm0_locked_i; --end if; --end process; process(tile0_rxusrclk21_i) begin if rxrecclk_dcm3_locked_i = '0' then TILE0RX_TMP_RST1 <= '0'; elsif tile0_rxusrclk21_i'event and tile0_rxusrclk21_i = '1' then if TILE0RX_TMP_RST1 = '0' then tile0_cnt1 <= tile0_cnt1 + '1'; if tile0_cnt1 < 7 then TILE0RX_RST1 <= '1'; elsif tile0_cnt1 = 7 then TILE0RX_RST1 <= '0'; tile0_cnt1 <= (others => '0'); TILE0RX_TMP_RST1 <= '1'; end if; end if; end if; end process; --process(tile0_rxusrclk21_i) --begin --if tile0_rxusrclk21_i'event and tile0_rxusrclk21_i = '1' then rxrecclk_dcm3_locked_out <= rxrecclk_dcm3_locked_i; --end if; --end process; process(tile1_rxusrclk20_i) begin if rxrecclk_dcm1_locked_i = '0' then TILE1RX_TMP_RST0 <= '0'; elsif tile1_rxusrclk20_i'event and tile1_rxusrclk20_i = '1' then if TILE1RX_TMP_RST0 = '0' then tile1_cnt0 <= tile1_cnt0 + '1'; if tile1_cnt0 < 7 then TILE1RX_RST0 <= '1'; elsif tile1_cnt0 = 7 then TILE1RX_RST0 <= '0'; tile1_cnt0 <= (others => '0'); TILE1RX_TMP_RST0 <= '1'; end if; end if; end if; end process; --process(tile1_rxusrclk20_i) --begin --if tile1_rxusrclk20_i'event and tile1_rxusrclk20_i = '1' then rxrecclk_dcm1_locked_out <= rxrecclk_dcm1_locked_i; --end if; --end process; process(tile1_rxusrclk21_i) begin if rxrecclk_dcm4_locked_i = '0' then TILE1RX_TMP_RST1 <= '0'; elsif tile1_rxusrclk21_i'event and tile1_rxusrclk21_i = '1' then if TILE1RX_TMP_RST1 = '0' then tile1_cnt1 <= tile1_cnt1 + '1'; if tile1_cnt1 < 7 then TILE1RX_RST1 <= '1'; elsif tile1_cnt1 = 7 then TILE1RX_RST1 <= '0'; tile1_cnt1 <= (others => '0'); TILE1RX_TMP_RST1 <= '1'; end if; end if; end if; end process; --process(tile1_rxusrclk21_i) --begin --if tile1_rxusrclk21_i'event and tile1_rxusrclk21_i = '1' then rxrecclk_dcm4_locked_out <= rxrecclk_dcm4_locked_i; --end if; --end process; p1:process(tile0_rxusrclk20_i) begin if tile0_rxusrclk20_i'event and tile0_rxusrclk20_i = '1' then TILE0_RXDATA0_OUT <= tile0_rxdata0_i; TILE0_RXCHARISK0_OUT <= tile0_rxcharisk0_i; end if; end process; p2:process(tile0_rxusrclk21_i) begin if tile0_rxusrclk21_i'event and tile0_rxusrclk21_i = '1' then TILE0_RXDATA1_OUT <= tile0_rxdata1_i; TILE0_RXCHARISK1_OUT<= tile0_rxcharisk1_i; end if; end process; p3:process(tile1_rxusrclk20_i) begin if tile1_rxusrclk20_i'event and tile1_rxusrclk20_i = '1' then TILE1_RXDATA0_OUT <= tile1_rxdata0_i; TILE1_RXCHARISK0_OUT<= tile1_rxcharisk0_i; end if; end process; p4:process(tile1_rxusrclk21_i) begin if tile1_rxusrclk21_i'event and tile1_rxusrclk21_i = '1' then TILE1_RXDATA1_OUT <= tile1_rxdata1_i; TILE1_RXCHARISK1_OUT<= tile1_rxcharisk1_i; end if; end process; TILE0_RXCLK0_OUT <= tile0_rxusrclk20_i; TILE0_RXCLK1_OUT <= tile0_rxusrclk21_i; TILE1_RXCLK0_OUT <= tile1_rxusrclk20_i; TILE1_RXCLK1_OUT <= tile1_rxusrclk21_i; TILE0_TXUSRCLK20_OUT <= tile0_txusrclk20_i; TILE1_TXUSRCLK20_OUT <= tile1_txusrclk20_i; tile0_resetdone0_i_out <= tile0_resetdone0_i; tile0_resetdone1_i_out <= tile0_resetdone1_i; tile1_resetdone0_i_out <= tile1_resetdone0_i; tile1_resetdone1_i_out <= tile1_resetdone1_i; tile0_refclkout_i_out <= tile0_refclkout_i; tile1_refclkout_i_out <= tile1_refclkout_i; tile0_rxlossofsync0_i_out <= tile0_rxlossofsync0_i; tile0_rxlossofsync1_i_out <= tile0_rxlossofsync1_i; tile1_rxlossofsync0_i_out <= tile1_rxlossofsync0_i; tile1_rxlossofsync1_i_out <= tile1_rxlossofsync1_i; tile0_rxchanrealign0_i_out <= tile0_rxchanrealign0_i; tile0_rxchanrealign1_i_out <= tile0_rxchanrealign1_i; tile1_rxchanrealign0_i_out <= tile1_rxchanrealign0_i; tile1_rxchanrealign1_i_out <= tile1_rxchanrealign1_i; tile0_rxchanisaligned0_i_out <= tile0_rxchanisaligned0_i; tile0_rxchanisaligned1_i_out <= tile0_rxchanisaligned1_i; tile1_rxchanisaligned0_i_out <= tile1_rxchanisaligned0_i; tile1_rxchanisaligned1_i_out <= tile1_rxchanisaligned1_i; tile0_rxbufstatus0_i_out <= tile0_rxbufstatus0_i; tile0_rxbufstatus1_i_out <= tile0_rxbufstatus1_i; tile1_rxbufstatus0_i_out <= tile1_rxbufstatus0_i; tile1_rxbufstatus1_i_out <= tile1_rxbufstatus1_i; tile0_rxcommadet0_i_out <= tile0_rxcommadet0_i; tile0_rxcommadet1_i_out <= tile0_rxcommadet1_i; tile1_rxcommadet0_i_out <= tile1_rxcommadet0_i; tile1_rxcommadet1_i_out <= tile1_rxcommadet1_i; tile0_rxbyterealign0_i_out <= tile0_rxbyterealign0_i; tile0_rxbyterealign1_i_out <= tile0_rxbyterealign1_i; tile1_rxbyterealign0_i_out <= tile1_rxbyterealign0_i; tile1_rxbyterealign1_i_out <= tile1_rxbyterealign1_i; tile0_rxbyteisaligned0_i_out <= tile0_rxbyteisaligned0_i; tile0_rxbyteisaligned1_i_out <= tile0_rxbyteisaligned1_i; tile1_rxbyteisaligned0_i_out <= tile1_rxbyteisaligned0_i; tile1_rxbyteisaligned1_i_out <= tile1_rxbyteisaligned1_i; tile0_rxnotintable0_i_out <= tile0_rxnotintable0_i; tile0_rxnotintable1_i_out <= tile0_rxnotintable1_i; tile1_rxnotintable0_i_out <= tile1_rxnotintable0_i; tile1_rxnotintable1_i_out <= tile1_rxnotintable1_i; tile0_rxdisperr0_i_out <= tile0_rxdisperr0_i; tile0_rxdisperr1_i_out <= tile0_rxdisperr1_i; tile1_rxdisperr0_i_out <= tile1_rxdisperr0_i; tile1_rxdisperr1_i_out <= tile1_rxdisperr1_i; tile0_rxchariscomma0_i_out <= tile0_rxchariscomma0_i; tile0_rxchariscomma1_i_out <= tile0_rxchariscomma1_i; tile1_rxchariscomma0_i_out <= tile1_rxchariscomma0_i; tile1_rxchariscomma1_i_out <= tile1_rxchariscomma1_i; end RTL;