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-- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA
-- File    : fifo_clk_gen1.vhd 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.numeric_std.all;

entity fifo_clk_gen1 is
    Port (     
	 clk_in   : in std_logic;
	 reset_in : in std_logic;
	 clk_out  : out std_logic;
	 clk200   : out std_logic;
	 lock_out : out std_logic
   );
end fifo_clk_gen1;
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architecture Behavioral of fifo_clk_gen1 is
signal clkdv, clk0,clkfb,clkfx : std_logic;
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begin
DCM_BASE_inst : DCM_BASE
   generic map (
      CLKDV_DIVIDE => 5.5, --7.0,to improve acqisition properly modified on 02222008 7.5, 
		-- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 5,   -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 6, -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 6.0, -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             --   an integer from 0 to 15
      DFS_FREQUENCY_MODE => "HIGH",   -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE => "HIGH",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
      PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
   port map (
	   CLK0 => clk0, ----- For the FIFO ---- 08Mar08	
      CLK180 => OPEN,     -- 180 degree DCM CLK output
      CLK270 => OPEN,     -- 270 degree DCM CLK output
      CLK2X => OPEN,       -- 2X DCM CLK output
      CLK2X180 => OPEN, -- 2X, 180 degree DCM CLK out
      CLK90 => OPEN,       -- 90 degree DCM CLK output
      CLKDV => clkdv,       -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => clkfx,       -- DCM CLK synthesis out (M/D)
      CLKFX180 => OPEN, -- 180 degree CLK synthesis out
      LOCKED => lock_out,     -- DCM LOCK status output
      CLKFB => clkfb,       -- DCM clock feedback
      CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
      RST => '0' --RST            -- DCM asynchronous reset input
 );

BUFG_clkfb_inst : BUFG
   port map (
      O => clkfb,     -- Clock buffer output
      I => clk0      -- Clock buffer input
   );

BUFG_clkdv_inst : BUFG
   port map (
      O => clk_out,     -- Clock buffer output
      I => clkdv      -- Clock buffer input
   );

BUFG_clkfx_inst : BUFG
   port map (
      O => clk200,     -- Clock buffer output
      I => clkfx      -- Clock buffer input
   );

End Behavioral;
---------- end of file : fifo_clk_gen1.vhd ----------------------
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