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--                        Raman Research Institute                            
--                            C V Raman Avenue                                 
--                             Sadashivanagar                                  
--                            Bangalore 560080                                 
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-- Project  : 12 metre backend                                                                	
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-- Designer : BSG and SV                                                                
-- Date     : June 1st 2003                                                                
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--                          Modification History                             	
--                         ~~~~~~~~~~~~~~~~~~~~~~                            	
-- Versions : 1.1                                                                
--                                                                           	
--                                                                           	
--                                                                           	
--                                                                           	
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-- Module   : ip_comm.vhd                                                                
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-- Module Description :                                                       

-- This module is a commutator based on 1024 outputs of a ring counter
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library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;
  

-- Ports Description  :                                                        
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entity ip_comm is
generic (com_width : integer := 1024);

 Port (
     CLK  : In  std_logic;
	  reset :In  std_logic;
	  FIR_EN: Out std_logic_vector( com_width-1 downto 0)        
     );
end ip_comm;


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-- Architecture Description  :                                                        

architecture ring_cnt of ip_comm is

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-- signal and variables Description  :                                                        
signal EN: std_logic_vector( com_width-1 downto 0); 
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begin 
	rng_cnt : process(CLK,reset) 
	begin 
    if( reset = '0') then
        EN(com_width-1 downto 1) <= (others => '0');
        EN(0) <= '1'; 
	 ELSIF(CLK'event and CLK = '1')then
        EN(com_width-1 downto 0) <=  EN(com_width-2 downto 0) &  EN(com_width-1)  ;
    end if;
    end  process rng_cnt;
	
	FIR_EN( com_width-1 DOWNTO 0) <= EN(com_width-1 DOWNTO 0);

end ring_cnt;

--end of  Architecture Description  
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