----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:31:49 07/21/2008 
-- Design Name: 
-- Module Name:    load_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity load_ram is
    Port ( clk_165 : in  STD_LOGIC;
			  clk_125 : in  STD_LOGIC;
			  rst : in STD_LOGIC;
           dina : in  STD_LOGIC_VECTOR (159 downto 0);	  
			  addra: IN std_logic_VECTOR(2 downto 0);	  
           wr_en : in  STD_LOGIC_VECTOR(0 downto 0);
		     addrb: IN std_logic_VECTOR(3 downto 0);		  
  			  rd_en : in STD_LOGIC;
--outputs			  
           dinb : out  STD_LOGIC_VECTOR (79 downto 0)
--           valid_data : out  STD_LOGIC
			);
end load_ram;

architecture load_ram_arc of load_ram is



component ram160
    port (
    clka: IN std_logic;
    dina: IN std_logic_VECTOR(159 downto 0);
    addra: IN std_logic_VECTOR(2 downto 0);
    ena: IN std_logic;
    wea: IN std_logic_VECTOR(0 downto 0);
    clkb: IN std_logic;
    addrb: IN std_logic_VECTOR(3 downto 0);
    enb: IN std_logic;
    doutb: OUT std_logic_VECTOR(79 downto 0));
end component;

begin

		ram160_inst : ram160
        port map (
            clka => clk_165,
				dina => dina,
            addra => addra,
            wea => wr_en,
            clkb => clk_125,
            addrb => addrb,
            enb => rd_en,
            doutb => dinb);


end load_ram_arc;