-------------------------------------------------------------- --
-- Project : ml402_sctn_distcard.ise        -- 21 OCT 2008 madhavi, kpa
-- File    : ml402_sctn_distcard_163MHz.vhd --with new freq 163.84MHz
----------------------------------------------------------------
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;
----------------------------------------------------------------
entity ml402_sctn_distcard_163MHz is
    Port ( 
			  CLK163		  : in std_logic;
  			  
			  tsctn1_fdce : out std_logic;
			  tsctn2_fdce : out std_logic 
			 );

end ml402_sctn_distcard_163MHz;
-----------------------------------------------------------------

architecture Behavioral of ml402_sctn_distcard_163MHz is

component rst_module1 
    Port ( 
	        clk_in    : in  STD_LOGIC;
			  ext_rst_in    : in std_logic;
	        ms6a_out  : out std_logic; 
			  reset_out : out std_logic);
end component;
------------ SIGNALS DECLARATION --------------------------------
------------- Signals -------------------------------------------
signal clk165a : std_logic := '0';
signal reset : std_logic := '0';
signal ctra : std_logic_vector(31 downto 0) := X"00000000";
signal tsctn1,tsctn2 : std_logic := '0';

SIGNAL led_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal xtal_clk125 : std_logic;
signal clk_lvds_in,clk_lvds,clk_lvds_bufg  : STD_LOGIC;
signal clk_in : std_logic := '0';
-----------------------------------------------------------------
-----------------------------------------------------------------
begin


reset_generate : rst_module1 
    Port map ( 
	        clk_in     => clk_lvds_in,
			  ext_rst_in => '0',
	        ms6a_out   => open, 
			  reset_out  => reset
			  );
-----------------------------------------------------------------

BUFG_clk_inst : BUFG
   port map (
      O => clk165a,     -- Clock buffer output
      I => CLK163      -- Clock buffer input
   );
-----------------------------------------------------------------
-----------------------------------------------------------------
---------- SCTN Generation --------------------------------------
-- tsctn1 is based on a 32 bit counter now used. 
process(clk165a)
begin 
 if(clk165a'event and clk165a='1') then
   if(reset = '1') then
     ctra <= X"00000000";
     tsctn1 <= '1';
	  tsctn2 <= '1';
   else
     ctra <= ctra + 1;
	       if (ctra = X"9C3FFFF") then -- 1 sec with 163.84e6 integral multiple of 128	  
--	       if (ctra = 32767) then -- 1 sec with 163.84e6 integral multiple of 128

----     if (ctra = X"09C40000") then -- 1 sec with 163.84e6 integral multiple of 128
--	  ----------------- Done here at ANU-RSAA, Anish, gk - 25sep08
----     if (ctra = X"09D593FF") then  -- ~1 sec with 165e6 integral multiple of 128
----	   if (ctra = X"28B0A") then  -- 1ms with 165e6 MHz clock
       tsctn1 <= '0';
	    tsctn2 <= '0';
		 ctra <= X"00000000";
		else
       tsctn1 <= '1';
	    tsctn2 <= '1';  
	  end if; 
   end if;	
 end if;
end process ;
------------ End of SCTN Generation -----------------------------
--------------- Single INIT Register tsctn1 ---------------------
FDCE_inst1 : FDCE
   generic map (
--      INIT => '0') -- Initial value of register ('0' or '1')  
      INIT => '1') -- Initial value of register ('0' or '1')  
   port map (
      Q => tsctn1_fdce,      -- Data output
      C => clk165a,      -- Clock input
      CE => '1',    -- Clock enable input
      CLR => '0',  -- RESET_IN,  -- Asynchronous clear input 
      D => tsctn1      -- Data input
   );
------------- Single INIT Register tsctn2 -----------------------
FDCE_inst2 : FDCE
   generic map (
--      INIT => '0') -- Initial value of register ('0' or '1')  
      INIT => '1') -- Initial value of register ('0' or '1')  
   port map (
      Q => tsctn2_fdce,      -- Data output
      C => clk165a,      -- Clock input
      CE => '1',    -- Clock enable input
      CLR => '0',  -- RESET_IN,  -- Asynchronous clear input
      D => tsctn2      -- Data input
   );


end Behavioral;

------------- end of file : sctn_distcard1.vhd ------------------