-----------------------------------------------------------------
-- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA
-- File : op_module1.vhd -- gk,  10032008
-- This module (op_fifo1.vhd) takes care of the output stage of 
-- the AgFo firmware (Ready for the VSIB DAS).
-----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.numeric_std.all;

entity op_module1 is
    Port (     
	 data_in          : in std_logic_vector(9 downto 0);
	 rd_clk_in        : in std_logic;
	 reset_in 		   : in std_logic;
	 vsib_pvalid_in 	: in std_logic;
	 vsib_trigger_in  : in std_logic;
	 
    DAS_OP_P : out std_logic_vector(9 downto 0);
    DAS_OP_N : out std_logic_vector(9 downto 0);
			  
	 DAS_trigger_P : out std_logic;
  	 DAS_trigger_N : out std_logic;
			  
  	 DAS_clk_P : out std_logic;
  	 DAS_clk_N : out std_logic;

	 DAS_pvalid_P : out std_logic;
  	 DAS_pvalid_N : out std_logic

   );
end op_module1;
-----------------------------------------------------------------
architecture Behavioral of op_module1 is

signal dinL1 : std_logic_vector(9 downto 0);
signal vsib_pvalidL1,vsib_triggerL1,vsib_clkL1 : std_logic := '0';

-----------------------------------------------------------------
begin
-----------------------------------------------------------------
-----------------------------------------------------------------
OP_LATCH:	FOR i IN 0 to 9 GENERATE 
BEGIN
   FDRSE_DATA_VSIB_inst_i : FDRSE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
   port map (
      Q => dinL1(i),      -- Data output 
      C => rd_clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      D => data_in(i),      -- Data input
      R => '0',      -- Synchronous reset input
      S => '0'       -- Synchronous set input
   );
END GENERATE;

FDRSE_vsib_trigger_inst : FDRSE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
   port map (
      Q => vsib_triggerL1,      -- Data output 
      C => rd_clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      D => vsib_trigger_in,      -- Data input
      R => '0',      -- Synchronous reset input
      S => '0'       -- Synchronous set input
   );
	
FDRSE_vsib_pvalid_inst : FDRSE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
   port map (
      Q => vsib_pvalidL1,      -- Data output 
      C => rd_clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      D => vsib_pvalid_in,      -- Data input
      R => '0',      -- Synchronous reset input
      S => '0'       -- Synchronous set input
   );

ODDR_rd_clk_inst : ODDR
   generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE
      INIT => '0',   -- Initial value for Q port ('1' or '0')
      SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
   port map (
      Q => vsib_clkL1,			-- 1-bit DDR output
      C => rd_clk_in,    					-- 1-bit clock input
      CE => '1',  					-- 1-bit clock enable input
      D1 => '1',  -- 1-bit data input (positive edge)
      D2 => '0', -- 1-bit data input (negative edge)
      R => reset_in,    			-- 1-bit reset input
      S => '0'     					-- 1-bit set input
   );
-----------------------------------------------------------------
---- Assignment of outputs for acquiring in DAS -----------------
   
	
OBUFDS_inst_i:	FOR i IN 0 to 9 GENERATE
BEGIN
OBUFDS_inst_i : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => DAS_OP_P(i),     -- Diff_p output (connect directly to top-level port)
      OB => DAS_OP_N(i),   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(i)     -- Buffer input 
   );
END GENERATE;
  
OBUFDS_inst1 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => DAS_trigger_P,     -- Diff_p output (connect directly to top-level port)
      OB => DAS_trigger_N,   -- Diff_n output (connect directly to top-level port)
--      I =>  vsib_pvalidL1     -- Buffer input 
      I =>  vsib_triggerL1     -- Buffer input -- CORRECT ONE - 20032008
   );
  
	OBUFDS_inst2 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => DAS_clk_P,     -- Diff_p output (connect directly to top-level port)
      OB => DAS_clk_N,   -- Diff_n output (connect directly to top-level port)
      I =>  vsib_clkL1     -- Buffer input 
   );
  
   OBUFDS_inst3 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => DAS_pvalid_P,     -- Diff_p output (connect directly to top-level port)
      OB => DAS_pvalid_N,   -- Diff_n output (connect directly to top-level port)
--      I =>  ENOUT     -- Buffer input 
--      I =>  vsib_triggerL1     -- Buffer input 
		I =>  vsib_pvalidL1     -- Buffer input  -- CORRECT ONE - 20032008
   );
-----------------------------------------------------------------  

end Behavioral;
-----------------------------------------------------------------
-------------- end of the file : op_module1.vhd -------------------