-----------------------------------------------------------------
-- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA
-- File : op_module2a.vhd -- gk,  10032008
-- This module (op_fifo1.vhd) takes care of the output stage of 
-- the AgFo firmware (Ready for the VSIB DAS).
-----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.numeric_std.all;

entity op_module2a is
    Port (     
			  data_in          : in std_logic_vector(9 downto 0);
			  rd_clk_in        : in std_logic;
			  reset_in 		    : in std_logic;
			  vsib_pvalid_in 	 : in std_logic;
			  vsib_trigger_in  : in std_logic;
	 
			  lv1_n				 : out  STD_LOGIC;
           lv1_p 				 : out  STD_LOGIC;
           lv2_n				 : out  STD_LOGIC;
           lv2_p				 : out  STD_LOGIC;
           lv3_n				 : out  STD_LOGIC;
           lv3_p				 : out  STD_LOGIC;
           lv4_n				 : out  STD_LOGIC;
           lv4_p 				 : out  STD_LOGIC;
           lv5_n				 : out  STD_LOGIC;
           lv5_p				 : out  STD_LOGIC;
           lv6_n				 : out  STD_LOGIC;
           lv6_p				 : out  STD_LOGIC;
           lv7_n				 : out  STD_LOGIC;
           lv7_p				 : out  STD_LOGIC;
           lv8_n				 : out  STD_LOGIC;
           lv8_p				 : out  STD_LOGIC;
           lv9_n				 : out  STD_LOGIC;
           lv9_p				 : out  STD_LOGIC;
           lv10_n				 : out  STD_LOGIC;
           lv10_p				 : out  STD_LOGIC;
           lv11_n				 : out  STD_LOGIC;
           lv11_p				 : out  STD_LOGIC;
           lv12_n 			 : out  STD_LOGIC;
           lv12_p 			 : out  STD_LOGIC;
           lv65_n 			 : out  STD_LOGIC;
           lv65_p			    : out  STD_LOGIC

   );
end op_module2a;
-----------------------------------------------------------------
architecture Behavioral of op_module2a is

signal dinL1 : std_logic_vector(9 downto 0);
signal vsib_pvalidL1,vsib_triggerL1,vsib_clkL1 : std_logic := '0';

-----------------------------------------------------------------
begin
-----------------------------------------------------------------
-----------------------------------------------------------------
OP_LATCH:	FOR i IN 0 to 9 GENERATE 
BEGIN
   FDRSE_DATA_VSIB_inst_i : FDRSE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
   port map (
      Q => dinL1(i),      -- Data output 
      C => rd_clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      D => data_in(i),      -- Data input
      R => '0',      -- Synchronous reset input
      S => '0'       -- Synchronous set input
   );
END GENERATE;

   
   OBUFDS_inst1 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv1_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv1_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(0)     -- Buffer input 
   );
  
	OBUFDS_inst2 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv2_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv2_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(1)     -- Buffer input 
   );
  
	OBUFDS_inst3 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv3_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv3_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(2)     -- Buffer input 
   );
  
	OBUFDS_inst4 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv4_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv4_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(3)     -- Buffer input 
   );
	
	OBUFDS_inst5 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv5_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv5_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(4)     -- Buffer input 
   );
	
	OBUFDS_inst6 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv6_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv6_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(5)     -- Buffer input 
   );
  
	OBUFDS_inst7 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv7_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv7_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(6)     -- Buffer input 
   );
  
   OBUFDS_inst8 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv8_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv8_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(7)     -- Buffer input 
   );
	
	OBUFDS_inst9 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv9_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv9_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(8)     -- Buffer input 
   );
  
	OBUFDS_inst10 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv10_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv10_n,   -- Diff_n output (connect directly to top-level port)
      I =>  dinL1(9)     -- Buffer input 
   );
  
----------------------------------------------------------------------------------	
FDRSE_vsib_pvalid_inst : FDRSE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
   port map (
      Q => vsib_pvalidL1,      -- Data output 
      C => rd_clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      D => vsib_pvalid_in,      -- Data input
      R => '0',      -- Synchronous reset input
      S => '0'       -- Synchronous set input
   );

OBUFDS_inst11 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv11_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv11_n,   -- Diff_n output (connect directly to top-level port)
--      I =>  vsib_pvalidL1     -- Buffer input 
      I =>  vsib_triggerL1     -- Buffer input 
 );
  ---------------------------------------------------------------------------------


ODDR_rd_clk_inst : ODDR
   generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE
      INIT => '0',   -- Initial value for Q port ('1' or '0')
      SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
   port map (
      Q => vsib_clkL1,			-- 1-bit DDR output
      C => rd_clk_in,    					-- 1-bit clock input
      CE => '1',  					-- 1-bit clock enable input
      D1 => '1',  -- 1-bit data input (positive edge)
      D2 => '0', -- 1-bit data input (negative edge)
      R => reset_in,    			-- 1-bit reset input
      S => '0'     					-- 1-bit set input
   );

OBUFDS_inst12 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv12_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv12_n,   -- Diff_n output (connect directly to top-level port)
      I =>  vsib_clkL1     -- Buffer input 
   );
  
---------------------------------------------------------------------------------------   


FDRSE_vsib_trigger_inst : FDRSE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
   port map (
      Q => vsib_triggerL1,      -- Data output 
      C => rd_clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      D => vsib_trigger_in,      -- Data input
      R => '0',      -- Synchronous reset input
      S => '0'       -- Synchronous set input
   );
   

   OBUFDS_inst13 : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => lv65_p,     -- Diff_p output (connect directly to top-level port)
      OB => lv65_n,   -- Diff_n output (connect directly to top-level port)
--      I =>  vsib_triggerL1     -- Buffer input 
      I =>  vsib_pvalidL1     -- Buffer input 

   );

-----------------------------------------------------------------  

end Behavioral;
-----------------------------------------------------------------
-------------- end of the file : op_module1.vhd -------------------