-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:30:39 02/06/2009 -- Design Name: optical_01 -- Module Name: D:/MWA_AGFOFIBRE_SIM_FEB08/MGTs/optical_TB.vhd -- Project Name: agfo12_b4_MGT -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: optical_01 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY optical_TB_vhd IS END optical_TB_vhd; ARCHITECTURE behavior OF optical_TB_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT optical_01 PORT( mgtck3_n : IN std_logic; mgtck3_p : IN std_logic; clkin : IN std_logic; rstin : IN std_logic; MGTRXP0_112 : IN std_logic; MGTRXN0_112 : IN std_logic; MGTRXN1_112 : IN std_logic; MGTRXP1_112 : IN std_logic; MGTREFCLKP_112 : IN std_logic; MGTREFCLKN_112 : IN std_logic; MGTRXP0_116 : IN std_logic; MGTRXN0_116 : IN std_logic; MGTRXN1_116 : IN std_logic; MGTRXP1_116 : IN std_logic; MGTREFCLKP_116 : IN std_logic; MGTREFCLKN_116 : IN std_logic; OPREG_RDEN : IN std_logic; RST_OPREG_LOAD : IN std_logic; read_reg : out STD_LOGIC_VECTOR(31 downto 0); usb_command : IN std_logic_vector(31 downto 0); valid_regceb : IN std_logic; valid_data : IN std_logic_vector(159 downto 0); MGTTXP0_112 : OUT std_logic; MGTTXN0_112 : OUT std_logic; MGTTXN1_112 : OUT std_logic; MGTTXP1_112 : OUT std_logic; MGTTXP0_116 : OUT std_logic; MGTTXN0_116 : OUT std_logic; MGTTXN1_116 : OUT std_logic; MGTTXP1_116 : OUT std_logic; -- lv1_n : OUT std_logic; -- lv1_p : OUT std_logic; -- lv2_n : OUT std_logic; -- lv2_p : OUT std_logic; -- lv3_n : OUT std_logic; -- lv3_p : OUT std_logic; -- lv4_n : OUT std_logic; -- lv4_p : OUT std_logic; -- lv5_n : OUT std_logic; -- lv5_p : OUT std_logic; -- lv6_n : OUT std_logic; -- lv6_p : OUT std_logic; -- lv7_n : OUT std_logic; -- lv7_p : OUT std_logic; -- lv8_n : OUT std_logic; -- lv8_p : OUT std_logic; -- lv9_n : OUT std_logic; -- lv9_p : OUT std_logic; -- lv10_n : OUT std_logic; -- lv10_p : OUT std_logic; -- lv11_n : OUT std_logic; -- lv11_p : OUT std_logic; -- lv12_n : OUT std_logic; -- lv12_p : OUT std_logic; -- lv65_n : OUT std_logic; -- lv65_p : OUT std_logic; system_reset_out : OUT std_logic -- read_reg : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs SIGNAL mgtck3_n : std_logic := '0'; SIGNAL mgtck3_p : std_logic := '0'; SIGNAL clkin : std_logic := '0'; SIGNAL rstin : std_logic := '0'; SIGNAL MGTRXP0_112 : std_logic := '0'; SIGNAL MGTRXN0_112 : std_logic := '0'; SIGNAL MGTRXN1_112 : std_logic := '0'; SIGNAL MGTRXP1_112 : std_logic := '0'; SIGNAL MGTREFCLKP_112 : std_logic := '0'; SIGNAL MGTREFCLKN_112 : std_logic := '0'; SIGNAL MGTRXP0_116 : std_logic := '0'; SIGNAL MGTRXN0_116 : std_logic := '0'; SIGNAL MGTRXN1_116 : std_logic := '0'; SIGNAL MGTRXP1_116 : std_logic := '0'; SIGNAL MGTREFCLKP_116 : std_logic := '0'; SIGNAL MGTREFCLKN_116 : std_logic := '0'; SIGNAL OPREG_RDEN : std_logic := '0'; SIGNAL RST_OPREG_LOAD : std_logic := '0'; SIGNAL valid_regceb : std_logic := '0'; SIGNAL usb_command , read_reg : std_logic_vector(31 downto 0) := (others=>'0'); SIGNAL valid_data : std_logic_vector(159 downto 0) := (others=>'0'); --Outputs SIGNAL MGTTXP0_112 : std_logic; SIGNAL MGTTXN0_112 : std_logic; SIGNAL MGTTXN1_112 : std_logic; SIGNAL MGTTXP1_112 : std_logic; SIGNAL MGTTXP0_116 : std_logic; SIGNAL MGTTXN0_116 : std_logic; SIGNAL MGTTXN1_116 : std_logic; SIGNAL MGTTXP1_116 : std_logic; -- SIGNAL lv1_n : std_logic; -- SIGNAL lv1_p : std_logic; -- SIGNAL lv2_n : std_logic; -- SIGNAL lv2_p : std_logic; -- SIGNAL lv3_n : std_logic; -- SIGNAL lv3_p : std_logic; -- SIGNAL lv4_n : std_logic; -- SIGNAL lv4_p : std_logic; -- SIGNAL lv5_n : std_logic; -- SIGNAL lv5_p : std_logic; -- SIGNAL lv6_n : std_logic; -- SIGNAL lv6_p : std_logic; -- SIGNAL lv7_n : std_logic; -- SIGNAL lv7_p : std_logic; -- SIGNAL lv8_n : std_logic; -- SIGNAL lv8_p : std_logic; -- SIGNAL lv9_n : std_logic; -- SIGNAL lv9_p : std_logic; -- SIGNAL lv10_n : std_logic; -- SIGNAL lv10_p : std_logic; -- SIGNAL lv11_n : std_logic; -- SIGNAL lv11_p : std_logic; -- SIGNAL lv12_n : std_logic; -- SIGNAL lv12_p : std_logic; -- SIGNAL lv65_n : std_logic; -- SIGNAL lv65_p : std_logic; SIGNAL system_reset_out : std_logic; SIGNAL clk_330MHz, clk165 : std_logic; component SIM_RESET_MGT_MODEL port ( GSR_IN : in std_logic ); end component; SIGNAL c1 : std_logic_vector(9 downto 0):=(others => '0'); BEGIN sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL port map ( GSR_IN => rstin ); -- Instantiate the Unit Under Test (UUT) uut: optical_01 PORT MAP( mgtck3_n => mgtck3_n, mgtck3_p => mgtck3_p, clkin => clkin, rstin => rstin, MGTTXP0_112 => MGTTXP0_112, MGTTXN0_112 => MGTTXN0_112, MGTRXP0_112 => MGTRXP0_112, MGTRXN0_112 => MGTRXN0_112, MGTRXN1_112 => MGTRXN1_112, MGTRXP1_112 => MGTRXP1_112, MGTTXN1_112 => MGTTXN1_112, MGTTXP1_112 => MGTTXP1_112, MGTREFCLKP_112 => MGTREFCLKP_112, MGTREFCLKN_112 => MGTREFCLKN_112, MGTTXP0_116 => MGTTXP0_116, MGTTXN0_116 => MGTTXN0_116, MGTRXP0_116 => MGTRXP0_116, MGTRXN0_116 => MGTRXN0_116, MGTRXN1_116 => MGTRXN1_116, MGTRXP1_116 => MGTRXP1_116, MGTTXN1_116 => MGTTXN1_116, MGTTXP1_116 => MGTTXP1_116, MGTREFCLKP_116 => MGTREFCLKP_116, MGTREFCLKN_116 => MGTREFCLKN_116, -- lv1_n => lv1_n, -- lv1_p => lv1_p, -- lv2_n => lv2_n, -- lv2_p => lv2_p, -- lv3_n => lv3_n, -- lv3_p => lv3_p, -- lv4_n => lv4_n, -- lv4_p => lv4_p, -- lv5_n => lv5_n, -- lv5_p => lv5_p, -- lv6_n => lv6_n, -- lv6_p => lv6_p, -- lv7_n => lv7_n, -- lv7_p => lv7_p, -- lv8_n => lv8_n, -- lv8_p => lv8_p, -- lv9_n => lv9_n, -- lv9_p => lv9_p, -- lv10_n => lv10_n, -- lv10_p => lv10_p, -- lv11_n => lv11_n, -- lv11_p => lv11_p, -- lv12_n => lv12_n, -- lv12_p => lv12_p, -- lv65_n => lv65_n, -- lv65_p => lv65_p, system_reset_out => system_reset_out, OPREG_RDEN => OPREG_RDEN, RST_OPREG_LOAD => RST_OPREG_LOAD, read_reg => read_reg, usb_command => usb_command, valid_regceb => valid_regceb, valid_data => valid_data ); rstin <= '1', '0' after 200 ns; -- process -- begin -- rstin <= '1'; -- wait for 200 ns; -- rstin <= '0'; -- wait; -- end process; clk_330: process -- Generate clock waveform of 330 MHz begin clk_330MHz<= '1', '0' after 1.5 ns, '1' after 3 ns, '0' after 4.5 ns; wait for 6 ns ; end process clk_330; clk_165: process -- Generate clock waveform of 330 MHz begin clk165<= '1', '0' after 4 ns, '1' after 8 ns, '0' after 12 ns; wait for 16 ns ; end process clk_165; --process(clk_330MHz) -- Generate clock waveform of 165 MHz -- begin -- if clk_330MHz'event and clk_330MHz = '1' then -- ctr_330 <= ctr_330+ '1' ; -- end if; --end process; --clk165 <= gc8_p; --gc8_p <= ctr_330(0); --gc8_n <= not ctr_330(0); --clk165 <= gc8_p; mgtck3_p <= clk165; mgtck3_n <= not clk165; MGTREFCLKP_112 <= clk165; MGTREFCLKN_112 <= not clk165; MGTREFCLKP_112 <= clk165; MGTREFCLKN_112 <= not clk165; MGTRXP0_112 <= MGTTXP0_112; MGTRXN0_112 <= MGTTXN0_112; MGTRXN1_112 <= MGTTXN1_112; MGTRXP1_112 <= MGTTXP1_112; MGTREFCLKP_116 <= clk165; MGTREFCLKN_116 <= not clk165; MGTRXP0_116 <= MGTTXP0_116; MGTRXN0_116 <= MGTTXN0_116; MGTRXN1_116 <= MGTTXN1_116; MGTRXP1_116 <= MGTTXP1_116; process(clk165) begin if clk165'event and clk165 = '1' then valid_regceb <= '1'; if valid_regceb = '1' then valid_regceb <= '0'; end if; end if; end process; clkin <= clk165; process(clk165) begin if clk165'event and clk165 = '1' then c1 <= c1 + '1' ; -- valid_regceb <= '1'; -- if valid_regceb = '1' then -- valid_regceb <= '0'; -- end if; end if; end process; valid_data <= c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1; END;