------------------------------------------------------------------------------- --$Date: 2007/08/01 23:10:49 $ --$RCSfile: multi_mgt_wrapper_vhd.ejava,v $ --$Revision: 1.1.2.1 $ ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 1.7 -- \ \ Application : GTP Wizard -- / / Filename : rocketio_wrapper.vhd -- /___/ /\ Timestamp : 02/08/2005 09:12:43 -- \ \ / \ -- \___\/\___\ -- -- -- Module ROCKETIO_WRAPPER (a GTP Wrapper) -- Generated by Xilinx GTP Wizard library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL; --***************************** Entity Declaration **************************** entity ROCKETIO_WRAPPER is generic ( -- Simulation attributes WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset WRAPPER_SIM_PLL_PERDIV2 : bit_vector:= x"190" -- Set to the VCO Unit Interval time ); port ( --_________________________________________________________________________ --_________________________________________________________________________ --TILE0 (Location) ------------------------ Loopback and Powerdown Ports ---------------------- TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0); TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0); TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE0_RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0); TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ TILE0_RXCHANBONDSEQ0_OUT : out std_logic; TILE0_RXCHANBONDSEQ1_OUT : out std_logic; TILE0_RXENCHANSYNC0_IN : in std_logic; TILE0_RXENCHANSYNC1_IN : in std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- TILE0_RXBYTEISALIGNED0_OUT : out std_logic; TILE0_RXBYTEISALIGNED1_OUT : out std_logic; TILE0_RXBYTEREALIGN0_OUT : out std_logic; TILE0_RXBYTEREALIGN1_OUT : out std_logic; TILE0_RXCOMMADET0_OUT : out std_logic; TILE0_RXCOMMADET1_OUT : out std_logic; TILE0_RXENMCOMMAALIGN0_IN : in std_logic; TILE0_RXENMCOMMAALIGN1_IN : in std_logic; TILE0_RXENPCOMMAALIGN0_IN : in std_logic; TILE0_RXENPCOMMAALIGN1_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE0_RXRECCLK0_OUT : out std_logic; TILE0_RXRECCLK1_OUT : out std_logic; TILE0_RXUSRCLK0_IN : in std_logic; TILE0_RXUSRCLK1_IN : in std_logic; TILE0_RXUSRCLK20_IN : in std_logic; TILE0_RXUSRCLK21_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE0_RXCDRRESET0_IN : in std_logic; TILE0_RXCDRRESET1_IN : in std_logic; TILE0_RXN0_IN : in std_logic; TILE0_RXN1_IN : in std_logic; TILE0_RXP0_IN : in std_logic; TILE0_RXP1_IN : in std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- TILE0_RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0); TILE0_RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0); TILE0_RXCHANISALIGNED0_OUT : out std_logic; TILE0_RXCHANISALIGNED1_OUT : out std_logic; TILE0_RXCHANREALIGN0_OUT : out std_logic; TILE0_RXCHANREALIGN1_OUT : out std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- TILE0_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0); TILE0_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- TILE0_CLKIN_IN : in std_logic; TILE0_GTPRESET_IN : in std_logic; TILE0_PLLLKDET_OUT : out std_logic; TILE0_REFCLKOUT_OUT : out std_logic; TILE0_RESETDONE0_OUT : out std_logic; TILE0_RESETDONE1_OUT : out std_logic; TILE0_TXENPMAPHASEALIGN_IN : in std_logic; TILE0_TXPMASETPHASE_IN : in std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0); TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0); TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0); TILE0_TXUSRCLK0_IN : in std_logic; TILE0_TXUSRCLK1_IN : in std_logic; TILE0_TXUSRCLK20_IN : in std_logic; TILE0_TXUSRCLK21_IN : in std_logic; --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE0_TXN0_OUT : out std_logic; TILE0_TXN1_OUT : out std_logic; TILE0_TXP0_OUT : out std_logic; TILE0_TXP1_OUT : out std_logic; --_________________________________________________________________________ --_________________________________________________________________________ --TILE1 (Location) ------------------------ Loopback and Powerdown Ports ---------------------- TILE1_LOOPBACK0_IN : in std_logic_vector(2 downto 0); TILE1_LOOPBACK1_IN : in std_logic_vector(2 downto 0); TILE1_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE1_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); TILE1_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TILE1_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- TILE1_RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); TILE1_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); TILE1_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); TILE1_RXDISPERR1_OUT : out std_logic_vector(1 downto 0); TILE1_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); TILE1_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ TILE1_RXCHANBONDSEQ0_OUT : out std_logic; TILE1_RXCHANBONDSEQ1_OUT : out std_logic; TILE1_RXENCHANSYNC0_IN : in std_logic; TILE1_RXENCHANSYNC1_IN : in std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- TILE1_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); TILE1_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- TILE1_RXBYTEISALIGNED0_OUT : out std_logic; TILE1_RXBYTEISALIGNED1_OUT : out std_logic; TILE1_RXBYTEREALIGN0_OUT : out std_logic; TILE1_RXBYTEREALIGN1_OUT : out std_logic; TILE1_RXCOMMADET0_OUT : out std_logic; TILE1_RXCOMMADET1_OUT : out std_logic; TILE1_RXENMCOMMAALIGN0_IN : in std_logic; TILE1_RXENMCOMMAALIGN1_IN : in std_logic; TILE1_RXENPCOMMAALIGN0_IN : in std_logic; TILE1_RXENPCOMMAALIGN1_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- TILE1_RXDATA0_OUT : out std_logic_vector(15 downto 0); TILE1_RXDATA1_OUT : out std_logic_vector(15 downto 0); TILE1_RXRECCLK0_OUT : out std_logic; TILE1_RXRECCLK1_OUT : out std_logic; TILE1_RXUSRCLK0_IN : in std_logic; TILE1_RXUSRCLK1_IN : in std_logic; TILE1_RXUSRCLK20_IN : in std_logic; TILE1_RXUSRCLK21_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ TILE1_RXCDRRESET0_IN : in std_logic; TILE1_RXCDRRESET1_IN : in std_logic; TILE1_RXN0_IN : in std_logic; TILE1_RXN1_IN : in std_logic; TILE1_RXP0_IN : in std_logic; TILE1_RXP1_IN : in std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- TILE1_RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0); TILE1_RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0); TILE1_RXCHANISALIGNED0_OUT : out std_logic; TILE1_RXCHANISALIGNED1_OUT : out std_logic; TILE1_RXCHANREALIGN0_OUT : out std_logic; TILE1_RXCHANREALIGN1_OUT : out std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- TILE1_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0); TILE1_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- TILE1_CLKIN_IN : in std_logic; TILE1_GTPRESET_IN : in std_logic; TILE1_PLLLKDET_OUT : out std_logic; TILE1_REFCLKOUT_OUT : out std_logic; TILE1_RESETDONE0_OUT : out std_logic; TILE1_RESETDONE1_OUT : out std_logic; TILE1_TXENPMAPHASEALIGN_IN : in std_logic; TILE1_TXPMASETPHASE_IN : in std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TILE1_TXCHARISK0_IN : in std_logic_vector(1 downto 0); TILE1_TXCHARISK1_IN : in std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- TILE1_TXDATA0_IN : in std_logic_vector(15 downto 0); TILE1_TXDATA1_IN : in std_logic_vector(15 downto 0); TILE1_TXUSRCLK0_IN : in std_logic; TILE1_TXUSRCLK1_IN : in std_logic; TILE1_TXUSRCLK20_IN : in std_logic; TILE1_TXUSRCLK21_IN : in std_logic; --------------- Transmit Ports - TX Driver and OOB signalling -------------- TILE1_TXN0_OUT : out std_logic; TILE1_TXN1_OUT : out std_logic; TILE1_TXP0_OUT : out std_logic; TILE1_TXP1_OUT : out std_logic; TXCHARDISPMODE0_1 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1_2 : in std_logic_vector(1 downto 0); TXCHARDISPMODE0_3 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1_4 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0_1 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1_2 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0_3 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1_4 : in std_logic_vector(1 downto 0); RXRESET0_IN1 : in std_logic; RXRESET0_IN2 : in std_logic; RXRESET0_IN3 : in std_logic; RXRESET0_IN4 : in std_logic; TXKERR0_1 : out std_logic_vector(1 downto 0); TXKERR1_2 : out std_logic_vector(1 downto 0); TXKERR0_3 : out std_logic_vector(1 downto 0); TXKERR1_4 : out std_logic_vector(1 downto 0); TXRUNDISP0_1 : out std_logic_vector(1 downto 0); TXRUNDISP1_2 : out std_logic_vector(1 downto 0); TXRUNDISP0_3 : out std_logic_vector(1 downto 0); TXRUNDISP1_4 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_1 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_2 : out std_logic_vector(1 downto 0); TXBUFSTATUS0_3 : out std_logic_vector(1 downto 0); TXBUFSTATUS1_4 : out std_logic_vector(1 downto 0); RXSTATUS0_1 : out std_logic_vector(2 downto 0); RXSTATUS1_2 : out std_logic_vector(2 downto 0); RXSTATUS0_3 : out std_logic_vector(2 downto 0); RXSTATUS1_4 : out std_logic_vector(2 downto 0); PHYSTATUS0_1 : out std_logic; PHYSTATUS1_2 : out std_logic; PHYSTATUS0_3 : out std_logic; PHYSTATUS1_4 : out std_logic; rxelecidle0_1 : out std_logic; rxelecidle1_2 : out std_logic; rxelecidle0_3 : out std_logic; rxelecidle1_4 : out std_logic; RXPRBSERR0_1 : out std_logic; RXPRBSERR1_2 : out std_logic; RXPRBSERR0_3 : out std_logic; RXPRBSERR1_4 : out std_logic; RXRUNDISP0_1 : out std_logic_vector(1 downto 0); RXRUNDISP1_2 : out std_logic_vector(1 downto 0); RXRUNDISP0_3 : out std_logic_vector(1 downto 0); RXRUNDISP1_4 : out std_logic_vector(1 downto 0) ); end ROCKETIO_WRAPPER; architecture RTL of ROCKETIO_WRAPPER is --***************************** Signal Declarations ***************************** -- Channel Bonding Signals signal tile0_rxchbondo0_i : std_logic_vector(2 downto 0); signal tile0_rxchbondo1_i : std_logic_vector(2 downto 0); signal tile1_rxchbondo0_i : std_logic_vector(2 downto 0); signal tile1_rxchbondo1_i : std_logic_vector(2 downto 0); -- ground and tied_to_vcc_i signals signal tied_to_ground_i : std_logic; signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); signal tied_to_vcc_i : std_logic; --***************************** Register Declarations ***************************** -- All TX inputs registered signal tile0_txcharisk0_r : std_logic_vector(1 downto 0); signal tile0_txdata0_r : std_logic_vector(15 downto 0); signal tile0_txcharisk1_r : std_logic_vector(1 downto 0); signal tile0_txdata1_r : std_logic_vector(15 downto 0); signal tile1_txcharisk0_r : std_logic_vector(1 downto 0); signal tile1_txdata0_r : std_logic_vector(15 downto 0); signal tile1_txcharisk1_r : std_logic_vector(1 downto 0); signal tile1_txdata1_r : std_logic_vector(15 downto 0); --*************************** Component Declarations ************************** component ROCKETIO_WRAPPER_TILE generic ( -- Simulation attributes TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset TILE_SIM_PLL_PERDIV2 : bit_vector:= x"190"; -- Set to the VCO Unit Interval time -- Channel bonding attributes TILE_CHAN_BOND_MODE_0 : string := "OFF"; -- "MASTER", "SLAVE", or "OFF" TILE_CHAN_BOND_LEVEL_0 : integer := 0; -- 0 to 7. See UG for details TILE_CHAN_BOND_MODE_1 : string := "OFF"; -- "MASTER", "SLAVE", or "OFF" TILE_CHAN_BOND_LEVEL_1 : integer := 0 -- 0 to 7. See UG for details ); port ( ------------------------ Loopback and Powerdown Ports ---------------------- LOOPBACK0_IN : in std_logic_vector(2 downto 0); LOOPBACK1_IN : in std_logic_vector(2 downto 0); RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0); RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0); RXCHARISK0_OUT : out std_logic_vector(1 downto 0); RXCHARISK1_OUT : out std_logic_vector(1 downto 0); RXDISPERR0_OUT : out std_logic_vector(1 downto 0); RXDISPERR1_OUT : out std_logic_vector(1 downto 0); RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); ------------------- Receive Ports - Channel Bonding Ports ------------------ RXCHANBONDSEQ0_OUT : out std_logic; RXCHANBONDSEQ1_OUT : out std_logic; RXCHBONDI0_IN : in std_logic_vector(2 downto 0); RXCHBONDI1_IN : in std_logic_vector(2 downto 0); RXCHBONDO0_OUT : out std_logic_vector(2 downto 0); RXCHBONDO1_OUT : out std_logic_vector(2 downto 0); RXENCHANSYNC0_IN : in std_logic; RXENCHANSYNC1_IN : in std_logic; ------------------- Receive Ports - Clock Correction Ports ----------------- RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- RXBYTEISALIGNED0_OUT : out std_logic; RXBYTEISALIGNED1_OUT : out std_logic; RXBYTEREALIGN0_OUT : out std_logic; RXBYTEREALIGN1_OUT : out std_logic; RXCOMMADET0_OUT : out std_logic; RXCOMMADET1_OUT : out std_logic; RXENMCOMMAALIGN0_IN : in std_logic; RXENMCOMMAALIGN1_IN : in std_logic; RXENPCOMMAALIGN0_IN : in std_logic; RXENPCOMMAALIGN1_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- RXDATA0_OUT : out std_logic_vector(15 downto 0); RXDATA1_OUT : out std_logic_vector(15 downto 0); RXRECCLK0_OUT : out std_logic; RXRECCLK1_OUT : out std_logic; RXUSRCLK0_IN : in std_logic; RXUSRCLK1_IN : in std_logic; RXUSRCLK20_IN : in std_logic; RXUSRCLK21_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ RXCDRRESET0_IN : in std_logic; RXCDRRESET1_IN : in std_logic; RXN0_IN : in std_logic; RXN1_IN : in std_logic; RXP0_IN : in std_logic; RXP1_IN : in std_logic; -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0); RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0); RXCHANISALIGNED0_OUT : out std_logic; RXCHANISALIGNED1_OUT : out std_logic; RXCHANREALIGN0_OUT : out std_logic; RXCHANREALIGN1_OUT : out std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0); --------------------- Shared Ports - Tile and PLL Ports -------------------- CLKIN_IN : in std_logic; GTPRESET_IN : in std_logic; PLLLKDET_OUT : out std_logic; REFCLKOUT_OUT : out std_logic; RESETDONE0_OUT : out std_logic; RESETDONE1_OUT : out std_logic; TXENPMAPHASEALIGN_IN : in std_logic; TXPMASETPHASE_IN : in std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TXCHARISK0_IN : in std_logic_vector(1 downto 0); TXCHARISK1_IN : in std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- TXDATA0_IN : in std_logic_vector(15 downto 0); TXDATA1_IN : in std_logic_vector(15 downto 0); TXUSRCLK0_IN : in std_logic; TXUSRCLK1_IN : in std_logic; TXUSRCLK20_IN : in std_logic; TXUSRCLK21_IN : in std_logic; --------------- Transmit Ports - TX Driver and OOB signalling -------------- TXN0_OUT : out std_logic; TXN1_OUT : out std_logic; TXP0_OUT : out std_logic; TXP1_OUT : out std_logic; TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); RXRESET0_IN : in std_logic; RXRESET1_IN : in std_logic; TXKERR0 : out std_logic_vector(1 downto 0); TXKERR1 : out std_logic_vector(1 downto 0); TXRUNDISP0 : out std_logic_vector(1 downto 0); TXRUNDISP1 : out std_logic_vector(1 downto 0); TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); PHYSTATUS0 : out std_logic; PHYSTATUS1 : out std_logic; rxelecidle0_i_OUT : out std_logic; rxelecidle1_i_OUT : out std_logic; RXPRBSERR0 : out std_logic; RXPRBSERR1 : out std_logic; RXRUNDISP0 : out std_logic_vector(1 downto 0); RXRUNDISP1 : out std_logic_vector(1 downto 0) ); end component; --*************************** MAXDELAY and LOC constraints ******************** ---------------------------------------------------------------------- --constraint for LX chip --attribute loc : string; -- attribute maxdelay : string; -- -- attribute loc of tile0_txcharisk0_r_0_i : label is "SLICE_X58Y76"; -- attribute loc of tile0_txcharisk0_r_1_i : label is "SLICE_X58Y76"; -- attribute loc of tile0_txdata0_r_0_i : label is "SLICE_X58Y76"; -- attribute loc of tile0_txdata0_r_1_i : label is "SLICE_X58Y76"; -- attribute loc of tile0_txdata0_r_2_i : label is "SLICE_X59Y76"; -- attribute loc of tile0_txdata0_r_3_i : label is "SLICE_X59Y76"; -- attribute loc of tile0_txdata0_r_4_i : label is "SLICE_X59Y76"; -- attribute loc of tile0_txdata0_r_5_i : label is "SLICE_X59Y76"; -- attribute loc of tile0_txdata0_r_6_i : label is "SLICE_X58Y77"; -- attribute loc of tile0_txdata0_r_7_i : label is "SLICE_X58Y77"; -- attribute loc of tile0_txdata0_r_8_i : label is "SLICE_X58Y77"; -- attribute loc of tile0_txdata0_r_9_i : label is "SLICE_X58Y77"; -- attribute loc of tile0_txdata0_r_10_i : label is "SLICE_X59Y77"; -- attribute loc of tile0_txdata0_r_11_i : label is "SLICE_X59Y77"; -- attribute loc of tile0_txdata0_r_12_i : label is "SLICE_X59Y77"; -- attribute loc of tile0_txdata0_r_13_i : label is "SLICE_X59Y77"; -- attribute loc of tile0_txdata0_r_14_i : label is "SLICE_X58Y78"; -- attribute loc of tile0_txdata0_r_15_i : label is "SLICE_X58Y78"; -- attribute loc of tile0_txcharisk1_r_0_i : label is "SLICE_X58Y60"; -- attribute loc of tile0_txcharisk1_r_1_i : label is "SLICE_X58Y60"; -- attribute loc of tile0_txdata1_r_0_i : label is "SLICE_X58Y60"; -- attribute loc of tile0_txdata1_r_1_i : label is "SLICE_X58Y60"; -- attribute loc of tile0_txdata1_r_2_i : label is "SLICE_X59Y60"; -- attribute loc of tile0_txdata1_r_3_i : label is "SLICE_X59Y60"; -- attribute loc of tile0_txdata1_r_4_i : label is "SLICE_X59Y60"; -- attribute loc of tile0_txdata1_r_5_i : label is "SLICE_X59Y60"; -- attribute loc of tile0_txdata1_r_6_i : label is "SLICE_X58Y61"; -- attribute loc of tile0_txdata1_r_7_i : label is "SLICE_X58Y61"; -- attribute loc of tile0_txdata1_r_8_i : label is "SLICE_X58Y61"; -- attribute loc of tile0_txdata1_r_9_i : label is "SLICE_X58Y61"; -- attribute loc of tile0_txdata1_r_10_i : label is "SLICE_X59Y61"; -- attribute loc of tile0_txdata1_r_11_i : label is "SLICE_X59Y61"; -- attribute loc of tile0_txdata1_r_12_i : label is "SLICE_X59Y61"; -- attribute loc of tile0_txdata1_r_13_i : label is "SLICE_X59Y61"; -- attribute loc of tile0_txdata1_r_14_i : label is "SLICE_X58Y62"; -- attribute loc of tile0_txdata1_r_15_i : label is "SLICE_X58Y62"; -- attribute loc of tile1_txcharisk0_r_0_i : label is "SLICE_X58Y96"; -- attribute loc of tile1_txcharisk0_r_1_i : label is "SLICE_X58Y96"; -- attribute loc of tile1_txdata0_r_0_i : label is "SLICE_X58Y96"; -- attribute loc of tile1_txdata0_r_1_i : label is "SLICE_X58Y96"; -- attribute loc of tile1_txdata0_r_2_i : label is "SLICE_X59Y96"; -- attribute loc of tile1_txdata0_r_3_i : label is "SLICE_X59Y96"; -- attribute loc of tile1_txdata0_r_4_i : label is "SLICE_X59Y96"; -- attribute loc of tile1_txdata0_r_5_i : label is "SLICE_X59Y96"; -- attribute loc of tile1_txdata0_r_6_i : label is "SLICE_X58Y97"; -- attribute loc of tile1_txdata0_r_7_i : label is "SLICE_X58Y97"; -- attribute loc of tile1_txdata0_r_8_i : label is "SLICE_X58Y97"; -- attribute loc of tile1_txdata0_r_9_i : label is "SLICE_X58Y97"; -- attribute loc of tile1_txdata0_r_10_i : label is "SLICE_X59Y97"; -- attribute loc of tile1_txdata0_r_11_i : label is "SLICE_X59Y97"; -- attribute loc of tile1_txdata0_r_12_i : label is "SLICE_X59Y97"; -- attribute loc of tile1_txdata0_r_13_i : label is "SLICE_X59Y97"; -- attribute loc of tile1_txdata0_r_14_i : label is "SLICE_X58Y98"; -- attribute loc of tile1_txdata0_r_15_i : label is "SLICE_X58Y98"; -- attribute loc of tile1_txcharisk1_r_0_i : label is "SLICE_X58Y80"; -- attribute loc of tile1_txcharisk1_r_1_i : label is "SLICE_X58Y80"; -- attribute loc of tile1_txdata1_r_0_i : label is "SLICE_X58Y80"; -- attribute loc of tile1_txdata1_r_1_i : label is "SLICE_X58Y80"; -- attribute loc of tile1_txdata1_r_2_i : label is "SLICE_X59Y80"; -- attribute loc of tile1_txdata1_r_3_i : label is "SLICE_X59Y80"; -- attribute loc of tile1_txdata1_r_4_i : label is "SLICE_X59Y80"; -- attribute loc of tile1_txdata1_r_5_i : label is "SLICE_X59Y80"; -- attribute loc of tile1_txdata1_r_6_i : label is "SLICE_X58Y81"; -- attribute loc of tile1_txdata1_r_7_i : label is "SLICE_X58Y81"; -- attribute loc of tile1_txdata1_r_8_i : label is "SLICE_X58Y81"; -- attribute loc of tile1_txdata1_r_9_i : label is "SLICE_X58Y81"; -- attribute loc of tile1_txdata1_r_10_i : label is "SLICE_X59Y81"; -- attribute loc of tile1_txdata1_r_11_i : label is "SLICE_X59Y81"; -- attribute loc of tile1_txdata1_r_12_i : label is "SLICE_X59Y81"; -- attribute loc of tile1_txdata1_r_13_i : label is "SLICE_X59Y81"; -- attribute loc of tile1_txdata1_r_14_i : label is "SLICE_X58Y82"; -- attribute loc of tile1_txdata1_r_15_i : label is "SLICE_X58Y82"; -- -- attribute maxdelay of tile0_txcharisk0_r : signal is "1"; -- attribute maxdelay of tile0_txdata0_r : signal is "1"; -- attribute maxdelay of tile0_txcharisk1_r : signal is "1"; -- attribute maxdelay of tile0_txdata1_r : signal is "1"; -- attribute maxdelay of tile1_txcharisk0_r : signal is "1"; -- attribute maxdelay of tile1_txdata0_r : signal is "1"; -- attribute maxdelay of tile1_txcharisk1_r : signal is "1"; -- attribute maxdelay of tile1_txdata1_r : signal is "1"; ---------------------------------------------------------------------- --constraint for SX chip attribute loc : string; attribute maxdelay : string; attribute loc of tile0_txcharisk0_r_0_i : label is "SLICE_X66Y76"; attribute loc of tile0_txcharisk0_r_1_i : label is "SLICE_X66Y76"; attribute loc of tile0_txdata0_r_0_i : label is "SLICE_X66Y76"; attribute loc of tile0_txdata0_r_1_i : label is "SLICE_X66Y76"; attribute loc of tile0_txdata0_r_2_i : label is "SLICE_X67Y76"; attribute loc of tile0_txdata0_r_3_i : label is "SLICE_X67Y76"; attribute loc of tile0_txdata0_r_4_i : label is "SLICE_X67Y76"; attribute loc of tile0_txdata0_r_5_i : label is "SLICE_X67Y76"; attribute loc of tile0_txdata0_r_6_i : label is "SLICE_X66Y77"; attribute loc of tile0_txdata0_r_7_i : label is "SLICE_X66Y77"; attribute loc of tile0_txdata0_r_8_i : label is "SLICE_X66Y77"; attribute loc of tile0_txdata0_r_9_i : label is "SLICE_X66Y77"; attribute loc of tile0_txdata0_r_10_i : label is "SLICE_X67Y77"; attribute loc of tile0_txdata0_r_11_i : label is "SLICE_X67Y77"; attribute loc of tile0_txdata0_r_12_i : label is "SLICE_X67Y77"; attribute loc of tile0_txdata0_r_13_i : label is "SLICE_X67Y77"; attribute loc of tile0_txdata0_r_14_i : label is "SLICE_X66Y78"; attribute loc of tile0_txdata0_r_15_i : label is "SLICE_X66Y78"; attribute loc of tile0_txcharisk1_r_0_i : label is "SLICE_X66Y60"; attribute loc of tile0_txcharisk1_r_1_i : label is "SLICE_X66Y60"; attribute loc of tile0_txdata1_r_0_i : label is "SLICE_X66Y60"; attribute loc of tile0_txdata1_r_1_i : label is "SLICE_X66Y60"; attribute loc of tile0_txdata1_r_2_i : label is "SLICE_X67Y60"; attribute loc of tile0_txdata1_r_3_i : label is "SLICE_X67Y60"; attribute loc of tile0_txdata1_r_4_i : label is "SLICE_X67Y60"; attribute loc of tile0_txdata1_r_5_i : label is "SLICE_X67Y60"; attribute loc of tile0_txdata1_r_6_i : label is "SLICE_X66Y61"; attribute loc of tile0_txdata1_r_7_i : label is "SLICE_X66Y61"; attribute loc of tile0_txdata1_r_8_i : label is "SLICE_X66Y61"; attribute loc of tile0_txdata1_r_9_i : label is "SLICE_X66Y61"; attribute loc of tile0_txdata1_r_10_i : label is "SLICE_X67Y61"; attribute loc of tile0_txdata1_r_11_i : label is "SLICE_X67Y61"; attribute loc of tile0_txdata1_r_12_i : label is "SLICE_X67Y61"; attribute loc of tile0_txdata1_r_13_i : label is "SLICE_X67Y61"; attribute loc of tile0_txdata1_r_14_i : label is "SLICE_X66Y62"; attribute loc of tile0_txdata1_r_15_i : label is "SLICE_X66Y62"; attribute loc of tile1_txcharisk0_r_0_i : label is "SLICE_X66Y96"; attribute loc of tile1_txcharisk0_r_1_i : label is "SLICE_X66Y96"; attribute loc of tile1_txdata0_r_0_i : label is "SLICE_X66Y96"; attribute loc of tile1_txdata0_r_1_i : label is "SLICE_X66Y96"; attribute loc of tile1_txdata0_r_2_i : label is "SLICE_X67Y96"; attribute loc of tile1_txdata0_r_3_i : label is "SLICE_X67Y96"; attribute loc of tile1_txdata0_r_4_i : label is "SLICE_X67Y96"; attribute loc of tile1_txdata0_r_5_i : label is "SLICE_X67Y96"; attribute loc of tile1_txdata0_r_6_i : label is "SLICE_X66Y97"; attribute loc of tile1_txdata0_r_7_i : label is "SLICE_X66Y97"; attribute loc of tile1_txdata0_r_8_i : label is "SLICE_X66Y97"; attribute loc of tile1_txdata0_r_9_i : label is "SLICE_X66Y97"; attribute loc of tile1_txdata0_r_10_i : label is "SLICE_X67Y97"; attribute loc of tile1_txdata0_r_11_i : label is "SLICE_X67Y97"; attribute loc of tile1_txdata0_r_12_i : label is "SLICE_X67Y97"; attribute loc of tile1_txdata0_r_13_i : label is "SLICE_X67Y97"; attribute loc of tile1_txdata0_r_14_i : label is "SLICE_X66Y98"; attribute loc of tile1_txdata0_r_15_i : label is "SLICE_X66Y98"; attribute loc of tile1_txcharisk1_r_0_i : label is "SLICE_X66Y80"; attribute loc of tile1_txcharisk1_r_1_i : label is "SLICE_X66Y80"; attribute loc of tile1_txdata1_r_0_i : label is "SLICE_X66Y80"; attribute loc of tile1_txdata1_r_1_i : label is "SLICE_X66Y80"; attribute loc of tile1_txdata1_r_2_i : label is "SLICE_X67Y80"; attribute loc of tile1_txdata1_r_3_i : label is "SLICE_X67Y80"; attribute loc of tile1_txdata1_r_4_i : label is "SLICE_X67Y80"; attribute loc of tile1_txdata1_r_5_i : label is "SLICE_X67Y80"; attribute loc of tile1_txdata1_r_6_i : label is "SLICE_X66Y81"; attribute loc of tile1_txdata1_r_7_i : label is "SLICE_X66Y81"; attribute loc of tile1_txdata1_r_8_i : label is "SLICE_X66Y81"; attribute loc of tile1_txdata1_r_9_i : label is "SLICE_X66Y81"; attribute loc of tile1_txdata1_r_10_i : label is "SLICE_X67Y81"; attribute loc of tile1_txdata1_r_11_i : label is "SLICE_X67Y81"; attribute loc of tile1_txdata1_r_12_i : label is "SLICE_X67Y81"; attribute loc of tile1_txdata1_r_13_i : label is "SLICE_X67Y81"; attribute loc of tile1_txdata1_r_14_i : label is "SLICE_X66Y82"; attribute loc of tile1_txdata1_r_15_i : label is "SLICE_X66Y82"; attribute maxdelay of tile0_txcharisk0_r : signal is "1"; attribute maxdelay of tile0_txdata0_r : signal is "1"; attribute maxdelay of tile0_txcharisk1_r : signal is "1"; attribute maxdelay of tile0_txdata1_r : signal is "1"; attribute maxdelay of tile1_txcharisk0_r : signal is "1"; attribute maxdelay of tile1_txdata0_r : signal is "1"; attribute maxdelay of tile1_txcharisk1_r : signal is "1"; attribute maxdelay of tile1_txdata1_r : signal is "1"; --********************************* Main Body of Code************************** begin tied_to_ground_i <= '0'; tied_to_ground_vec_i(63 downto 0) <= (others => '0'); tied_to_vcc_i <= '1'; --------------------------- Tile Instances ------------------------------- ---------------------- Register GTP0 TX inputs for TILE0 ----------------- tile0_txcharisk0_r_0_i : FD port map(D=>TILE0_TXCHARISK0_IN(0),Q=>tile0_txcharisk0_r(0),C=>TILE0_TXUSRCLK20_IN); tile0_txcharisk0_r_1_i : FD port map(D=>TILE0_TXCHARISK0_IN(1),Q=>tile0_txcharisk0_r(1),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_0_i : FD port map(D=>TILE0_TXDATA0_IN(0),Q=>tile0_txdata0_r(0),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_1_i : FD port map(D=>TILE0_TXDATA0_IN(1),Q=>tile0_txdata0_r(1),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_2_i : FD port map(D=>TILE0_TXDATA0_IN(2),Q=>tile0_txdata0_r(2),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_3_i : FD port map(D=>TILE0_TXDATA0_IN(3),Q=>tile0_txdata0_r(3),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_4_i : FD port map(D=>TILE0_TXDATA0_IN(4),Q=>tile0_txdata0_r(4),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_5_i : FD port map(D=>TILE0_TXDATA0_IN(5),Q=>tile0_txdata0_r(5),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_6_i : FD port map(D=>TILE0_TXDATA0_IN(6),Q=>tile0_txdata0_r(6),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_7_i : FD port map(D=>TILE0_TXDATA0_IN(7),Q=>tile0_txdata0_r(7),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_8_i : FD port map(D=>TILE0_TXDATA0_IN(8),Q=>tile0_txdata0_r(8),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_9_i : FD port map(D=>TILE0_TXDATA0_IN(9),Q=>tile0_txdata0_r(9),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_10_i : FD port map(D=>TILE0_TXDATA0_IN(10),Q=>tile0_txdata0_r(10),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_11_i : FD port map(D=>TILE0_TXDATA0_IN(11),Q=>tile0_txdata0_r(11),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_12_i : FD port map(D=>TILE0_TXDATA0_IN(12),Q=>tile0_txdata0_r(12),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_13_i : FD port map(D=>TILE0_TXDATA0_IN(13),Q=>tile0_txdata0_r(13),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_14_i : FD port map(D=>TILE0_TXDATA0_IN(14),Q=>tile0_txdata0_r(14),C=>TILE0_TXUSRCLK20_IN); tile0_txdata0_r_15_i : FD port map(D=>TILE0_TXDATA0_IN(15),Q=>tile0_txdata0_r(15),C=>TILE0_TXUSRCLK20_IN); ---------------------- Register GTP1 TX inputs for TILE0 ----------------- tile0_txcharisk1_r_0_i : FD port map(D=>TILE0_TXCHARISK1_IN(0),Q=>tile0_txcharisk1_r(0),C=>TILE0_TXUSRCLK21_IN); tile0_txcharisk1_r_1_i : FD port map(D=>TILE0_TXCHARISK1_IN(1),Q=>tile0_txcharisk1_r(1),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_0_i : FD port map(D=>TILE0_TXDATA1_IN(0),Q=>tile0_txdata1_r(0),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_1_i : FD port map(D=>TILE0_TXDATA1_IN(1),Q=>tile0_txdata1_r(1),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_2_i : FD port map(D=>TILE0_TXDATA1_IN(2),Q=>tile0_txdata1_r(2),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_3_i : FD port map(D=>TILE0_TXDATA1_IN(3),Q=>tile0_txdata1_r(3),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_4_i : FD port map(D=>TILE0_TXDATA1_IN(4),Q=>tile0_txdata1_r(4),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_5_i : FD port map(D=>TILE0_TXDATA1_IN(5),Q=>tile0_txdata1_r(5),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_6_i : FD port map(D=>TILE0_TXDATA1_IN(6),Q=>tile0_txdata1_r(6),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_7_i : FD port map(D=>TILE0_TXDATA1_IN(7),Q=>tile0_txdata1_r(7),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_8_i : FD port map(D=>TILE0_TXDATA1_IN(8),Q=>tile0_txdata1_r(8),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_9_i : FD port map(D=>TILE0_TXDATA1_IN(9),Q=>tile0_txdata1_r(9),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_10_i : FD port map(D=>TILE0_TXDATA1_IN(10),Q=>tile0_txdata1_r(10),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_11_i : FD port map(D=>TILE0_TXDATA1_IN(11),Q=>tile0_txdata1_r(11),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_12_i : FD port map(D=>TILE0_TXDATA1_IN(12),Q=>tile0_txdata1_r(12),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_13_i : FD port map(D=>TILE0_TXDATA1_IN(13),Q=>tile0_txdata1_r(13),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_14_i : FD port map(D=>TILE0_TXDATA1_IN(14),Q=>tile0_txdata1_r(14),C=>TILE0_TXUSRCLK21_IN); tile0_txdata1_r_15_i : FD port map(D=>TILE0_TXDATA1_IN(15),Q=>tile0_txdata1_r(15),C=>TILE0_TXUSRCLK21_IN); --_________________________________________________________________________ --_________________________________________________________________________ --TILE0 (Location) tile0_rocketio_wrapper_i : ROCKETIO_WRAPPER_TILE generic map ( -- Simulation attributes TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP, TILE_SIM_PLL_PERDIV2 => WRAPPER_SIM_PLL_PERDIV2, -- Channel bonding attributes TILE_CHAN_BOND_MODE_0 => "MASTER", TILE_CHAN_BOND_LEVEL_0 => 2, TILE_CHAN_BOND_MODE_1 => "SLAVE", TILE_CHAN_BOND_LEVEL_1 => 1 ) port map ( ------------------------ Loopback and Powerdown Ports ---------------------- LOOPBACK0_IN => TILE0_LOOPBACK0_IN, LOOPBACK1_IN => TILE0_LOOPBACK1_IN, RXPOWERDOWN0_IN => TILE0_RXPOWERDOWN0_IN, RXPOWERDOWN1_IN => TILE0_RXPOWERDOWN1_IN, TXPOWERDOWN0_IN => TILE0_TXPOWERDOWN0_IN, TXPOWERDOWN1_IN => TILE0_TXPOWERDOWN1_IN, ----------------------- Receive Ports - 8b10b Decoder ---------------------- RXCHARISCOMMA0_OUT => TILE0_RXCHARISCOMMA0_OUT, RXCHARISCOMMA1_OUT => TILE0_RXCHARISCOMMA1_OUT, RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT, RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT, RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT, RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT, RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT, RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT, ------------------- Receive Ports - Channel Bonding Ports ------------------ RXCHANBONDSEQ0_OUT => TILE0_RXCHANBONDSEQ0_OUT, RXCHANBONDSEQ1_OUT => TILE0_RXCHANBONDSEQ1_OUT, RXCHBONDI0_IN => tied_to_ground_vec_i(2 downto 0), RXCHBONDI1_IN => tile1_rxchbondo0_i, RXCHBONDO0_OUT => tile1_rxchbondo0_i, RXCHBONDO1_OUT => tile1_rxchbondo1_i, RXENCHANSYNC0_IN => TILE0_RXENCHANSYNC0_IN, RXENCHANSYNC1_IN => TILE0_RXENCHANSYNC1_IN, ------------------- Receive Ports - Clock Correction Ports ----------------- RXCLKCORCNT0_OUT => TILE0_RXCLKCORCNT0_OUT, RXCLKCORCNT1_OUT => TILE0_RXCLKCORCNT1_OUT, --------------- Receive Ports - Comma Detection and Alignment -------------- RXBYTEISALIGNED0_OUT => TILE0_RXBYTEISALIGNED0_OUT, RXBYTEISALIGNED1_OUT => TILE0_RXBYTEISALIGNED1_OUT, RXBYTEREALIGN0_OUT => TILE0_RXBYTEREALIGN0_OUT, RXBYTEREALIGN1_OUT => TILE0_RXBYTEREALIGN1_OUT, RXCOMMADET0_OUT => TILE0_RXCOMMADET0_OUT, RXCOMMADET1_OUT => TILE0_RXCOMMADET1_OUT, RXENMCOMMAALIGN0_IN => TILE0_RXENMCOMMAALIGN0_IN, RXENMCOMMAALIGN1_IN => TILE0_RXENMCOMMAALIGN1_IN, RXENPCOMMAALIGN0_IN => TILE0_RXENPCOMMAALIGN0_IN, RXENPCOMMAALIGN1_IN => TILE0_RXENPCOMMAALIGN1_IN, ------------------- Receive Ports - RX Data Path interface ----------------- RXDATA0_OUT => TILE0_RXDATA0_OUT, RXDATA1_OUT => TILE0_RXDATA1_OUT, RXRECCLK0_OUT => TILE0_RXRECCLK0_OUT, RXRECCLK1_OUT => TILE0_RXRECCLK1_OUT, RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN, RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN, RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN, RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ RXCDRRESET0_IN => TILE0_RXCDRRESET0_IN, RXCDRRESET1_IN => TILE0_RXCDRRESET1_IN, RXN0_IN => TILE0_RXN0_IN, RXN1_IN => TILE0_RXN1_IN, RXP0_IN => TILE0_RXP0_IN, RXP1_IN => TILE0_RXP1_IN, -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- RXBUFSTATUS0_OUT => TILE0_RXBUFSTATUS0_OUT, RXBUFSTATUS1_OUT => TILE0_RXBUFSTATUS1_OUT, RXCHANISALIGNED0_OUT => TILE0_RXCHANISALIGNED0_OUT, RXCHANISALIGNED1_OUT => TILE0_RXCHANISALIGNED1_OUT, RXCHANREALIGN0_OUT => TILE0_RXCHANREALIGN0_OUT, RXCHANREALIGN1_OUT => TILE0_RXCHANREALIGN1_OUT, --------------- Receive Ports - RX Loss-of-sync State Machine -------------- RXLOSSOFSYNC0_OUT => TILE0_RXLOSSOFSYNC0_OUT, RXLOSSOFSYNC1_OUT => TILE0_RXLOSSOFSYNC1_OUT, --------------------- Shared Ports - Tile and PLL Ports -------------------- CLKIN_IN => TILE0_CLKIN_IN, GTPRESET_IN => TILE0_GTPRESET_IN, PLLLKDET_OUT => TILE0_PLLLKDET_OUT, REFCLKOUT_OUT => TILE0_REFCLKOUT_OUT, RESETDONE0_OUT => TILE0_RESETDONE0_OUT, RESETDONE1_OUT => TILE0_RESETDONE1_OUT, TXENPMAPHASEALIGN_IN => TILE0_TXENPMAPHASEALIGN_IN, TXPMASETPHASE_IN => TILE0_TXPMASETPHASE_IN, ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TXCHARISK0_IN => tile0_txcharisk0_r, TXCHARISK1_IN => tile0_txcharisk1_r, ------------------ Transmit Ports - TX Data Path interface ----------------- TXDATA0_IN => tile0_txdata0_r, TXDATA1_IN => tile0_txdata1_r, TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN, TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN, TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN, TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN, --------------- Transmit Ports - TX Driver and OOB signalling -------------- TXN0_OUT => TILE0_TXN0_OUT, TXN1_OUT => TILE0_TXN1_OUT, TXP0_OUT => TILE0_TXP0_OUT, TXP1_OUT => TILE0_TXP1_OUT, TXCHARDISPMODE0 => TXCHARDISPMODE0_1, TXCHARDISPMODE1 => TXCHARDISPMODE1_2, TXCHARDISPVAL0 => TXCHARDISPVAL0_1, TXCHARDISPVAL1 => TXCHARDISPVAL1_2, RXRESET0_IN => RXRESET0_IN1, RXRESET1_IN => RXRESET0_IN2, TXKERR0 => TXKERR0_1, TXKERR1 => TXKERR1_2, TXRUNDISP0 => TXRUNDISP0_1, TXRUNDISP1 => TXRUNDISP1_2, TXBUFSTATUS0 => TXBUFSTATUS0_1, TXBUFSTATUS1 => TXBUFSTATUS1_2, RXSTATUS0 => RXSTATUS0_1, RXSTATUS1 => RXSTATUS1_2, PHYSTATUS0 => PHYSTATUS0_1, PHYSTATUS1 => PHYSTATUS1_2, rxelecidle0_i_OUT => rxelecidle0_1, rxelecidle1_i_OUT => rxelecidle1_2, RXPRBSERR0 => RXPRBSERR0_1, RXPRBSERR1 => RXPRBSERR1_2, RXRUNDISP0 => RXRUNDISP0_1, RXRUNDISP1 => RXRUNDISP1_2 ); ---------------------- Register GTP0 TX inputs for TILE1 ----------------- tile1_txcharisk0_r_0_i : FD port map(D=>TILE1_TXCHARISK0_IN(0),Q=>tile1_txcharisk0_r(0),C=>TILE1_TXUSRCLK20_IN); tile1_txcharisk0_r_1_i : FD port map(D=>TILE1_TXCHARISK0_IN(1),Q=>tile1_txcharisk0_r(1),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_0_i : FD port map(D=>TILE1_TXDATA0_IN(0),Q=>tile1_txdata0_r(0),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_1_i : FD port map(D=>TILE1_TXDATA0_IN(1),Q=>tile1_txdata0_r(1),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_2_i : FD port map(D=>TILE1_TXDATA0_IN(2),Q=>tile1_txdata0_r(2),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_3_i : FD port map(D=>TILE1_TXDATA0_IN(3),Q=>tile1_txdata0_r(3),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_4_i : FD port map(D=>TILE1_TXDATA0_IN(4),Q=>tile1_txdata0_r(4),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_5_i : FD port map(D=>TILE1_TXDATA0_IN(5),Q=>tile1_txdata0_r(5),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_6_i : FD port map(D=>TILE1_TXDATA0_IN(6),Q=>tile1_txdata0_r(6),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_7_i : FD port map(D=>TILE1_TXDATA0_IN(7),Q=>tile1_txdata0_r(7),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_8_i : FD port map(D=>TILE1_TXDATA0_IN(8),Q=>tile1_txdata0_r(8),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_9_i : FD port map(D=>TILE1_TXDATA0_IN(9),Q=>tile1_txdata0_r(9),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_10_i : FD port map(D=>TILE1_TXDATA0_IN(10),Q=>tile1_txdata0_r(10),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_11_i : FD port map(D=>TILE1_TXDATA0_IN(11),Q=>tile1_txdata0_r(11),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_12_i : FD port map(D=>TILE1_TXDATA0_IN(12),Q=>tile1_txdata0_r(12),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_13_i : FD port map(D=>TILE1_TXDATA0_IN(13),Q=>tile1_txdata0_r(13),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_14_i : FD port map(D=>TILE1_TXDATA0_IN(14),Q=>tile1_txdata0_r(14),C=>TILE1_TXUSRCLK20_IN); tile1_txdata0_r_15_i : FD port map(D=>TILE1_TXDATA0_IN(15),Q=>tile1_txdata0_r(15),C=>TILE1_TXUSRCLK20_IN); ---------------------- Register GTP1 TX inputs for TILE1 ----------------- tile1_txcharisk1_r_0_i : FD port map(D=>TILE1_TXCHARISK1_IN(0),Q=>tile1_txcharisk1_r(0),C=>TILE1_TXUSRCLK21_IN); tile1_txcharisk1_r_1_i : FD port map(D=>TILE1_TXCHARISK1_IN(1),Q=>tile1_txcharisk1_r(1),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_0_i : FD port map(D=>TILE1_TXDATA1_IN(0),Q=>tile1_txdata1_r(0),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_1_i : FD port map(D=>TILE1_TXDATA1_IN(1),Q=>tile1_txdata1_r(1),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_2_i : FD port map(D=>TILE1_TXDATA1_IN(2),Q=>tile1_txdata1_r(2),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_3_i : FD port map(D=>TILE1_TXDATA1_IN(3),Q=>tile1_txdata1_r(3),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_4_i : FD port map(D=>TILE1_TXDATA1_IN(4),Q=>tile1_txdata1_r(4),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_5_i : FD port map(D=>TILE1_TXDATA1_IN(5),Q=>tile1_txdata1_r(5),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_6_i : FD port map(D=>TILE1_TXDATA1_IN(6),Q=>tile1_txdata1_r(6),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_7_i : FD port map(D=>TILE1_TXDATA1_IN(7),Q=>tile1_txdata1_r(7),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_8_i : FD port map(D=>TILE1_TXDATA1_IN(8),Q=>tile1_txdata1_r(8),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_9_i : FD port map(D=>TILE1_TXDATA1_IN(9),Q=>tile1_txdata1_r(9),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_10_i : FD port map(D=>TILE1_TXDATA1_IN(10),Q=>tile1_txdata1_r(10),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_11_i : FD port map(D=>TILE1_TXDATA1_IN(11),Q=>tile1_txdata1_r(11),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_12_i : FD port map(D=>TILE1_TXDATA1_IN(12),Q=>tile1_txdata1_r(12),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_13_i : FD port map(D=>TILE1_TXDATA1_IN(13),Q=>tile1_txdata1_r(13),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_14_i : FD port map(D=>TILE1_TXDATA1_IN(14),Q=>tile1_txdata1_r(14),C=>TILE1_TXUSRCLK21_IN); tile1_txdata1_r_15_i : FD port map(D=>TILE1_TXDATA1_IN(15),Q=>tile1_txdata1_r(15),C=>TILE1_TXUSRCLK21_IN); --_________________________________________________________________________ --_________________________________________________________________________ --TILE1 (Location) tile1_rocketio_wrapper_i : ROCKETIO_WRAPPER_TILE generic map ( -- Simulation attributes TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP, TILE_SIM_PLL_PERDIV2 => WRAPPER_SIM_PLL_PERDIV2, -- Channel bonding attributes TILE_CHAN_BOND_MODE_0 => "SLAVE", TILE_CHAN_BOND_LEVEL_0 => 0, TILE_CHAN_BOND_MODE_1 => "SLAVE", TILE_CHAN_BOND_LEVEL_1 => 0 ) port map ( ------------------------ Loopback and Powerdown Ports ---------------------- LOOPBACK0_IN => TILE1_LOOPBACK0_IN, LOOPBACK1_IN => TILE1_LOOPBACK1_IN, RXPOWERDOWN0_IN => TILE1_RXPOWERDOWN0_IN, RXPOWERDOWN1_IN => TILE1_RXPOWERDOWN1_IN, TXPOWERDOWN0_IN => TILE1_TXPOWERDOWN0_IN, TXPOWERDOWN1_IN => TILE1_TXPOWERDOWN1_IN, ----------------------- Receive Ports - 8b10b Decoder ---------------------- RXCHARISCOMMA0_OUT => TILE1_RXCHARISCOMMA0_OUT, RXCHARISCOMMA1_OUT => TILE1_RXCHARISCOMMA1_OUT, RXCHARISK0_OUT => TILE1_RXCHARISK0_OUT, RXCHARISK1_OUT => TILE1_RXCHARISK1_OUT, RXDISPERR0_OUT => TILE1_RXDISPERR0_OUT, RXDISPERR1_OUT => TILE1_RXDISPERR1_OUT, RXNOTINTABLE0_OUT => TILE1_RXNOTINTABLE0_OUT, RXNOTINTABLE1_OUT => TILE1_RXNOTINTABLE1_OUT, ------------------- Receive Ports - Channel Bonding Ports ------------------ RXCHANBONDSEQ0_OUT => TILE1_RXCHANBONDSEQ0_OUT, RXCHANBONDSEQ1_OUT => TILE1_RXCHANBONDSEQ1_OUT, RXCHBONDI0_IN => tile1_rxchbondo1_i, RXCHBONDI1_IN => tile1_rxchbondo1_i, RXCHBONDO0_OUT => tile0_rxchbondo0_i, RXCHBONDO1_OUT => tile0_rxchbondo1_i, RXENCHANSYNC0_IN => TILE1_RXENCHANSYNC0_IN, RXENCHANSYNC1_IN => TILE1_RXENCHANSYNC1_IN, ------------------- Receive Ports - Clock Correction Ports ----------------- RXCLKCORCNT0_OUT => TILE1_RXCLKCORCNT0_OUT, RXCLKCORCNT1_OUT => TILE1_RXCLKCORCNT1_OUT, --------------- Receive Ports - Comma Detection and Alignment -------------- RXBYTEISALIGNED0_OUT => TILE1_RXBYTEISALIGNED0_OUT, RXBYTEISALIGNED1_OUT => TILE1_RXBYTEISALIGNED1_OUT, RXBYTEREALIGN0_OUT => TILE1_RXBYTEREALIGN0_OUT, RXBYTEREALIGN1_OUT => TILE1_RXBYTEREALIGN1_OUT, RXCOMMADET0_OUT => TILE1_RXCOMMADET0_OUT, RXCOMMADET1_OUT => TILE1_RXCOMMADET1_OUT, RXENMCOMMAALIGN0_IN => TILE1_RXENMCOMMAALIGN0_IN, RXENMCOMMAALIGN1_IN => TILE1_RXENMCOMMAALIGN1_IN, RXENPCOMMAALIGN0_IN => TILE1_RXENPCOMMAALIGN0_IN, RXENPCOMMAALIGN1_IN => TILE1_RXENPCOMMAALIGN1_IN, ------------------- Receive Ports - RX Data Path interface ----------------- RXDATA0_OUT => TILE1_RXDATA0_OUT, RXDATA1_OUT => TILE1_RXDATA1_OUT, RXRECCLK0_OUT => TILE1_RXRECCLK0_OUT, RXRECCLK1_OUT => TILE1_RXRECCLK1_OUT, RXUSRCLK0_IN => TILE1_RXUSRCLK0_IN, RXUSRCLK1_IN => TILE1_RXUSRCLK1_IN, RXUSRCLK20_IN => TILE1_RXUSRCLK20_IN, RXUSRCLK21_IN => TILE1_RXUSRCLK21_IN, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ RXCDRRESET0_IN => TILE1_RXCDRRESET0_IN, RXCDRRESET1_IN => TILE1_RXCDRRESET1_IN, RXN0_IN => TILE1_RXN0_IN, RXN1_IN => TILE1_RXN1_IN, RXP0_IN => TILE1_RXP0_IN, RXP1_IN => TILE1_RXP1_IN, -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- RXBUFSTATUS0_OUT => TILE1_RXBUFSTATUS0_OUT, RXBUFSTATUS1_OUT => TILE1_RXBUFSTATUS1_OUT, RXCHANISALIGNED0_OUT => TILE1_RXCHANISALIGNED0_OUT, RXCHANISALIGNED1_OUT => TILE1_RXCHANISALIGNED1_OUT, RXCHANREALIGN0_OUT => TILE1_RXCHANREALIGN0_OUT, RXCHANREALIGN1_OUT => TILE1_RXCHANREALIGN1_OUT, --------------- Receive Ports - RX Loss-of-sync State Machine -------------- RXLOSSOFSYNC0_OUT => TILE1_RXLOSSOFSYNC0_OUT, RXLOSSOFSYNC1_OUT => TILE1_RXLOSSOFSYNC1_OUT, --------------------- Shared Ports - Tile and PLL Ports -------------------- CLKIN_IN => TILE1_CLKIN_IN, GTPRESET_IN => TILE1_GTPRESET_IN, PLLLKDET_OUT => TILE1_PLLLKDET_OUT, REFCLKOUT_OUT => TILE1_REFCLKOUT_OUT, RESETDONE0_OUT => TILE1_RESETDONE0_OUT, RESETDONE1_OUT => TILE1_RESETDONE1_OUT, TXENPMAPHASEALIGN_IN => TILE1_TXENPMAPHASEALIGN_IN, TXPMASETPHASE_IN => TILE1_TXPMASETPHASE_IN, ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TXCHARISK0_IN => tile1_txcharisk0_r, TXCHARISK1_IN => tile1_txcharisk1_r, ------------------ Transmit Ports - TX Data Path interface ----------------- TXDATA0_IN => tile1_txdata0_r, TXDATA1_IN => tile1_txdata1_r, TXUSRCLK0_IN => TILE1_TXUSRCLK0_IN, TXUSRCLK1_IN => TILE1_TXUSRCLK1_IN, TXUSRCLK20_IN => TILE1_TXUSRCLK20_IN, TXUSRCLK21_IN => TILE1_TXUSRCLK21_IN, --------------- Transmit Ports - TX Driver and OOB signalling -------------- TXN0_OUT => TILE1_TXN0_OUT, TXN1_OUT => TILE1_TXN1_OUT, TXP0_OUT => TILE1_TXP0_OUT, TXP1_OUT => TILE1_TXP1_OUT, TXCHARDISPMODE0 => TXCHARDISPMODE0_3, TXCHARDISPMODE1 => TXCHARDISPMODE1_4, TXCHARDISPVAL0 => TXCHARDISPVAL0_3, TXCHARDISPVAL1 => TXCHARDISPVAL1_4, RXRESET0_IN => RXRESET0_IN3, RXRESET1_IN => RXRESET0_IN4, TXKERR0 => TXKERR0_3, TXKERR1 => TXKERR1_4, TXRUNDISP0 => TXRUNDISP0_3, TXRUNDISP1 => TXRUNDISP1_4, TXBUFSTATUS0 => TXBUFSTATUS0_3, TXBUFSTATUS1 => TXBUFSTATUS1_4, RXSTATUS0 => RXSTATUS0_3, RXSTATUS1 => RXSTATUS1_4, PHYSTATUS0 => PHYSTATUS0_3, PHYSTATUS1 => PHYSTATUS1_4, rxelecidle0_i_OUT => rxelecidle0_3, rxelecidle1_i_OUT => rxelecidle1_4, RXPRBSERR0 => RXPRBSERR0_3, RXPRBSERR1 => RXPRBSERR1_4, RXRUNDISP0 => RXRUNDISP0_3, RXRUNDISP1 => RXRUNDISP1_4 ); end RTL;