----------------------------------------------------------------
-- Project : sctn_distcard1.ise -- 17062008-RRI-RAL-crater-gk
-- Projet : rst_module1.ise   19Jan2008-Sat-crater
-- File   : rst_module1.vhd / .ise
----------------------------------------------------------------
-- This module provides RESET_PULSE - 0 for RESETing the system
--                                    1 for NORMAL WORKING

-- This module provides RESET_ONCE  - 1 for RESETing the system
--                                    0 for NORMAL WORKING
----- This happens ONLY ONCE -----------------------------------

-- There will be 1 counter which will take the RESET from the INIT
-- based 16 bit shift register.
--  gk, 17Jan2008
----------------------------------------------------------------
-- Company: RAMAN RESEARCH INSTITUTE
-- Engineer: gk
 
-- Create Date:    19:40:52 01/17/2008 
-- Design Name:  
-- Module Name:    rst_module1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity rst_module1 is
    Port ( 
      	  clk_in    : in  STD_LOGIC;
			  ext_rst_in    : in std_logic;
	        ms6a_out  : out std_logic; 
			  reset_out : out std_logic);
end rst_module1;

architecture Behavioral of rst_module1 is

signal counter1 : std_logic_vector(15 downto 0) := X"0000";
signal reset1,reset2,ext_rst1,s_ext_rst : std_logic := '0';
signal ms1,init_anded,rst_control,reset_once : std_logic := '0';

signal Q15 : std_logic ;
signal a0 : std_logic := '1';
signal a1 : std_logic := '1';
signal a2 : std_logic := '1';
signal a3 : std_logic := '1';
signal RESET_VALUE : std_logic_vector(15 downto 0):=X"FFFE";
--signal RESET_VALUE : std_logic_vector(15 downto 0):=X"0010";


begin
------------ External RESET Input double synchronization ---------
--------------- Single INIT Register with 0 ----------------------
 FDCE_inst1 : FDCE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
--      INIT => '1') -- Initial value of register ('0' or '1')  
   port map (
      Q => ext_rst1,      -- Data output
      C => clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      CLR => '0',  -- RESET_IN,  -- Asynchronous clear input
      D => ext_rst_in      -- Data input
   );
------------- Single INIT Register with 0 ----------------------
 FDCE_inst2 : FDCE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
--      INIT => '1') -- Initial value of register ('0' or '1')  
   port map (
      Q => s_ext_rst,      -- Data output
      C => clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      CLR => '0',  -- RESET_IN,  -- Asynchronous clear input
      D => ext_rst1      -- Data input
   );
----------------------------------------------------------------
------------------ 16 bit shift register -----------------------
   SRLC16E_inst : SRLC16E
   generic map (
      INIT => X"FFFF")
   port map (
      Q => reset1,       -- SRL data output
--      Q15 => DATA_OUT0,   -- Carry output (connect to next SRL)
      Q15 => Q15,   -- Carry output (connect to next SRL)
      A0 => A0,     -- Select[0] input
      A1 => A1,     -- Select[1] input
      A2 => A2,     -- Select[2] input
      A3 => A3,     -- Select[3] input
--      CE => CE,     -- Clock enable input
      CE => '1',     -- Clock enable input
      CLK => clk_in,   -- Clock input
      D => '0'         -- SRL data input
--      D => D        -- SRL data input
   );

------------- Single INIT Register with 0 ----------------------
 FDCE_inst3 : FDCE
   generic map (
      INIT => '0') -- Initial value of register ('0' or '1')  
--      INIT => '1') -- Initial value of register ('0' or '1')  
   port map (
      Q => reset2,      -- Data output
      C => clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      CLR => '0',  -- RESET_IN,  -- Asynchronous clear input
      D => reset1      -- Data input
   );
----------------------------------------------------------------
-- 16-bit counter1 - UP COUNTER --------------------------------
-- and reset pulse generation 
process(clk_in)
begin
 if(clk_in'event and clk_in = '1') then
--  if( (reset1 = '1') or (s_ext_rst='1') ) then  ---- *** ----
  if( (reset2 = '1') or (s_ext_rst='1') ) then  ---- *** ----
    counter1 <= x"0000";
	 ms1 <= '1';
  elsif(counter1 = RESET_VALUE) then
    ms1 <= '0';
    counter1 <= counter1 + 1;
  else  
    ms1 <= '1';
    counter1 <= counter1 + 1;
  end if;	 
 else
  counter1 <= counter1; 
 end if; 
end process;
------------- Single INIT Register with 1 ----------------------
 FDCE_inst : FDCE
   generic map (
--      INIT => '0') -- Initial value of register ('0' or '1')  
      INIT => '1') -- Initial value of register ('0' or '1')  
   port map (
      Q => reset_once,      -- Data output
      C => clk_in,      -- Clock input
      CE => '1',    -- Clock enable input
      CLR => '0',  -- RESET_IN,  -- Asynchronous clear input
      D => rst_control      -- Data input
   );
----------------------------------------------------------------
init_anded  <= reset_once and ms1;
--rst_control <= init_anded or reset1 ;
--rst_control <= init_anded or reset1 or s_ext_rst ;
rst_control <= init_anded or reset2 or s_ext_rst ;

reset_out <= reset_once;
ms6a_out <= ms1;
--counter_out <= counter1;

end Behavioral;

----------- end of file : rst_module1.vhd -----------------------