---------------------------------------------------------------- -- Projet : rst_module1.ise 19Jan2008-Sat-crater -- File : rst_module1.vhd / .ise ---------------------------------------------------------------- -- This module provides RESET_PULSE - 0 for RESETing the system -- 1 for NORMAL WORKING -- This module provides RESET_ONCE - 1 for RESETing the system -- 0 for NORMAL WORKING ----- This happens ONLY ONCE ----------------------------------- -- There will be 1 counter which will take the RESET from the INIT -- based 16 bit shift register. -- gk, 17Jan2008 ---------------------------------------------------------------- -- Company: RAMAN RESEARCH INSTITUTE -- Engineer: gk -- Create Date: 19:40:52 01/17/2008 -- Design Name: -- Module Name: rst_module1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity rst_module1_usb is Port ( clk_in : in STD_LOGIC; -- ext_rst_in : in std_logic; usb_data_in : in std_logic_vector(31 downto 0); usb_load : in std_logic; refclkout_pll2_locked_out: in std_logic; refclkout_pll5_locked_out: in std_logic; rxrecclk_dcm0_locked_out : in std_logic; rxrecclk_dcm3_locked_out : in std_logic; rxrecclk_dcm1_locked_out : in std_logic; rxrecclk_dcm4_locked_out : in std_logic; -- counter_out : out std_logic_vector(15 downto 0); ms6a_out : out std_logic; reset_out : out std_logic; MGT_RESET : out std_logic; GLOBAL_RESET : out std_logic; rx1_RESET : out std_logic; rx2_RESET : out std_logic; rx3_RESET : out std_logic; rx4_RESET : out std_logic ); end rst_module1_usb; architecture Behavioral of rst_module1_usb is signal counter1,counter2,counter2_g : std_logic_vector(15 downto 0) := X"0000"; signal reset1,reset2,ext_rst1,s_ext_rst,m_ext_rst,mgt_rst1 : std_logic := '0'; signal ms1,ms2: std_logic; signal reset_once,reset_once_mgt : std_logic := '1'; signal Q15 ,ext_rst_in,ext_rst_internal,mgt_rst_in,mgt_rst_internal: std_logic ; signal a0 : std_logic := '1'; signal a1 : std_logic := '1'; signal a2 : std_logic := '1'; signal a3 : std_logic := '1'; signal check_ld_low,usb_load_int,valid_load: std_logic := '0'; signal reset_reg : std_logic_vector(31 downto 0):=(OTHERS => '0'); signal ext_rst_internal_ctr,mgt_rst_internal_ctr,global_rst_internal_ctr : std_logic_vector(3 downto 0):=(others => '0'); signal global_rst_in,global_ext_rst,MGT_PLL_LOCK ,global_rst_internal,temp_rst: std_logic; signal ms2_g,int_sig,global_rst1 : std_logic; signal rx1_counter2_g,rx2_counter2_g : std_logic_vector(15 downto 0) := X"0000"; signal rx3_counter2_g,rx4_counter2_g : std_logic_vector(15 downto 0) := X"0000"; signal rx1_ms2_g,rx2_ms2_g : std_logic; signal rx3_ms2_g,rx4_ms2_g : std_logic; signal rx1_rst_internal_ctr,rx2_rst_internal_ctr : std_logic_vector(3 downto 0):=(others => '0'); signal rx3_rst_internal_ctr,rx4_rst_internal_ctr : std_logic_vector(3 downto 0):=(others => '0'); signal rx1_rst_internal,rx2_rst_internal : std_logic; signal rx3_rst_internal,rx4_rst_internal : std_logic; signal rx1_rst_in,rx2_rst_in,rx1_ext_rst,rx2_ext_rst: std_logic; signal rx3_rst_in,rx4_rst_in,rx3_ext_rst,rx4_ext_rst: std_logic; signal rx1_rst_in1,rx2_rst_in1,rx1_int_sig,rx2_int_sig: std_logic; signal rx3_rst_in1,rx4_rst_in1,rx3_int_sig,rx4_int_sig: std_logic; --signal RESET_VALUE : std_logic_vector(15 downto 0):=X"0010"; signal RESET_VALUE : std_logic_vector(15 downto 0):=X"FFFE"; begin --usb valid load process(clk_in) begin if clk_in'event and clk_in= '1' then usb_load_int <= usb_load; if usb_load_int = '1' and check_ld_low = '0' then valid_load <= '1'; check_ld_low <= '1'; elsif usb_load_int = '1' and check_ld_low = '1' then valid_load <= valid_load ; check_ld_low <= check_ld_low; elsif usb_load_int = '0' and check_ld_low = '1' then check_ld_low<= '0'; valid_load <= valid_load; elsif usb_load_int = '0' and check_ld_low = '0' then valid_load <= valid_load ; check_ld_low<= '0';--check_ld_low; end if; if valid_load = '1' then valid_load <= '0'; end if; end if; end process; --========================================================================= ---------------------------------------------------------------------------- -- usb RESET with POWER ON process(clk_in,valid_load) begin if clk_in'event and clk_in = '1' then if ext_rst_in = '1' or mgt_rst_in = '1' or global_rst_in = '1' or reset2 = '1' or rx1_rst_in = '1' or rx2_rst_in = '1' or rx3_rst_in = '1' or rx4_rst_in = '1' then reset_reg <= (others => '0'); elsif valid_load = '1' then reset_reg <= usb_data_in; else reset_reg <= reset_reg; end if; if ext_rst_internal = '1' and reset2 = '0' then ext_rst_in <= '1'; ext_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then ext_rst_in <= '0'; end if; if ext_rst_in = '1' then ext_rst_internal_ctr <= ext_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if ext_rst_internal_ctr = 10 then ext_rst_in <= '0'; ext_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; ext_rst_internal <= reset_reg(0); ------------ External RESET Input double synchronization --------- --------------- Single INIT Register with 0 ---------------------- FDCE_inst1 : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => ext_rst1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => ext_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- FDCE_inst2 : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => s_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => ext_rst1 -- Data input ); ---------------------------------------------------------------- ------------------ 16 bit shift register ----------------------- SRLC16E_inst : SRLC16E generic map ( INIT => X"FFFF") port map ( Q => reset1, -- SRL data output -- Q15 => DATA_OUT0, -- Carry output (connect to next SRL) Q15 => Q15, -- Carry output (connect to next SRL) A0 => A0, -- Select[0] input A1 => A1, -- Select[1] input A2 => A2, -- Select[2] input A3 => A3, -- Select[3] input -- CE => CE, -- Clock enable input CE => '1', -- Clock enable input CLK => clk_in, -- Clock input D => '0' -- SRL data input -- D => D -- SRL data input ); ------------- Single INIT Register with 0 ---------------------- FDCE_inst3 : FDCE generic map ( INIT => '1') -- Initial value of register ('0' or '1') -- Anish Feb 23, 2008 -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => reset2, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => reset1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then -- if( (reset1 = '1') or (s_ext_rst='1') ) then ---- *** ---- if( (reset2 = '1') or (s_ext_rst='1') ) then ---- *** ---- counter1 <= x"0000"; ms1 <= '1'; elsif(counter1 = RESET_VALUE) then --for simulation this value is reduced to 28F ms1 <= '0'; counter1 <= counter1 + 1; else ms1 <= '1'; counter1 <= counter1 + 1; end if; else counter1 <= counter1; end if; end process; ------------- Single INIT Register with 1 ---------------------- FDCE_inst : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => reset_out, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => reset_once -- Data input ); --init_anded <= reset_once and ms1; --rst_control <= init_anded or reset2 or s_ext_rst ; ms6a_out <= ms1; process(clk_in) begin if(clk_in'event and clk_in = '1') then reset_once <= (reset_once and ms1) or reset2 or s_ext_rst ; end if; end process; --========================================================================= ---------------------------------------------------------------------------------------------- -- MGT RESET Section--31.03.09 process(clk_in,valid_load) begin if clk_in'event and clk_in = '1' then if mgt_rst_internal = '1' and reset2 = '0' then mgt_rst_in <= '1'; mgt_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then mgt_rst_in <= '0'; end if; if mgt_rst_in = '1' then mgt_rst_internal_ctr <= mgt_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if mgt_rst_internal_ctr = 10 then mgt_rst_in <= '0'; mgt_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; mgt_rst_internal <= reset_reg(1); ------------ External RESET Input double synchronization --------- --------------- Single INIT Register with 0 ---------------------- FDCE_inst5 : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => mgt_rst1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => mgt_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- FDCE_inst6 : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => m_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => mgt_rst1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then -- if( (reset1 = '1') or (s_ext_rst='1') ) then ---- *** ---- if( (reset2 = '1') or (m_ext_rst='1') ) then ---- *** ---- counter2 <= x"0000"; ms2 <= '1'; elsif(counter2 = RESET_VALUE) then --for simulation this value is reduced to 28F ms2 <= '0'; counter2 <= counter2 + 1; else ms2 <= '1'; counter2 <= counter2 + 1; end if; else counter2 <= counter2; end if; end process; FDCE_instmgt : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => MGT_RESET, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => reset_once_mgt -- Data input ); --init_anded <= reset_once and ms1; --rst_control <= init_anded or reset2 or s_ext_rst ; process(clk_in) begin if(clk_in'event and clk_in = '1') then reset_once_mgt <= (reset_once_mgt and ms2) or reset2 or m_ext_rst ; -- reset_once_mgt <= m_ext_rst ; end if; end process; ---------------------------------------------------------------------------- --========================================================================== -- generation of COMMON RESET w.r.t the MGTs PLL LOCKS process(clk_in,valid_load) begin if clk_in'event and clk_in = '1' then if reset_once_mgt = '1' then MGT_PLL_LOCK <= '0'; else MGT_PLL_LOCK <= refclkout_pll2_locked_out and refclkout_pll5_locked_out and rxrecclk_dcm0_locked_out and rxrecclk_dcm3_locked_out and rxrecclk_dcm1_locked_out and rxrecclk_dcm4_locked_out ; end if; if global_rst_internal = '1' and reset2 = '0' then global_rst_in <= '1'; global_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then global_rst_in <= '0'; end if; if global_rst_in = '1' then --and temp_rst = '0' then global_rst_internal_ctr <= global_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if global_rst_internal_ctr = 10 then global_rst_in <= '0'; global_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; global_rst_internal <= reset_reg(2); ------------ External RESET Input double synchronization --------- --------------- Single INIT Register with 0 ---------------------- FDCE_inst5a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => global_rst1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => global_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- FDCE_inst6a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => global_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => global_rst1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then if reset_once_mgt = '1' or MGT_PLL_LOCK = '0' or global_ext_rst = '1' then int_sig <= '0'; counter2_g <= (others => '0'); ms2_g <= '0'; elsif MGT_PLL_LOCK = '1' and int_sig = '0' then counter2_g <= counter2_g + 1; if(counter2_g < RESET_VALUE) then ms2_g <= '1'; elsif(counter2_g = RESET_VALUE) then ms2_g <= '0'; counter2_g <= (others => '0'); int_sig <= '1'; end if; -- if int_sig = '1' and global_ext_rst = '1' then -- int_sig <= '0' ; -- end if; end if; end if; end process; FDCE_instmgta : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => GLOBAL_RESET, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => ms2_g -- Data input ); ----------------------------------------- --RX1 RESET for tile0 process(clk_in,valid_load) begin if clk_in'event and clk_in = '1' then if rx1_rst_internal = '1' and reset2 = '0' then rx1_rst_in <= '1'; rx1_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then rx1_rst_in <= '0'; end if; if rx1_rst_in = '1' then --and temp_rst = '0' then rx1_rst_internal_ctr <= rx1_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if rx1_rst_internal_ctr = 10 then rx1_rst_in <= '0'; rx1_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; rx1_rst_internal <= reset_reg(3); --------------- Single INIT Register with 0 ---------------------- rx1FDCE_inst5a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx1_rst_in1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx1_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- rx1FDCE_inst6a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx1_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx1_rst_in1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then if rx1_ext_rst = '1' then rx1_int_sig <= '0'; rx1_counter2_g <= (others => '0'); rx1_ms2_g <= '0'; elsif MGT_PLL_LOCK = '1' and rx1_int_sig = '0' then rx1_counter2_g <= rx1_counter2_g + 1; if(rx1_counter2_g < RESET_VALUE) then rx1_ms2_g <= '1'; elsif(rx1_counter2_g = RESET_VALUE) then rx1_ms2_g <= '0'; rx1_counter2_g <= (others => '0'); rx1_int_sig <= '1'; end if; end if; end if; end process; rx1FDCE_instmgta : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => RX1_RESET, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx1_ms2_g -- Data input ); --------------------------------------------------------------- --RX2 RESET for tile0 process(clk_in) begin if clk_in'event and clk_in = '1' then if rx2_rst_internal = '1' and reset2 = '0' then rx2_rst_in <= '1'; rx2_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then rx2_rst_in <= '0'; end if; if rx2_rst_in = '1' then --and temp_rst = '0' then rx2_rst_internal_ctr <= rx2_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if rx2_rst_internal_ctr = 10 then rx2_rst_in <= '0'; rx2_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; rx2_rst_internal <= reset_reg(4); --------------- Single INIT Register with 0 ---------------------- rx2FDCE_inst5a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx2_rst_in1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx2_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- rx2FDCE_inst6a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx2_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx2_rst_in1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then if rx2_ext_rst = '1' then rx2_int_sig <= '0'; rx2_counter2_g <= (others => '0'); rx2_ms2_g <= '0'; elsif MGT_PLL_LOCK = '1' and rx2_int_sig = '0' then rx2_counter2_g <= rx2_counter2_g + 1; if(rx2_counter2_g < RESET_VALUE) then rx2_ms2_g <= '1'; elsif(rx2_counter2_g = RESET_VALUE) then rx2_ms2_g <= '0'; rx2_counter2_g <= (others => '0'); rx2_int_sig <= '1'; end if; end if; end if; end process; rx2FDCE_instmgta : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => rx2_RESET, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx2_ms2_g -- Data input ); -------------------------------------------------------------------------- --------------------------------------------------------------- --RX3 RESET for tile1 process(clk_in) begin if clk_in'event and clk_in = '1' then if rx3_rst_internal = '1' and reset2 = '0' then rx3_rst_in <= '1'; rx3_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then rx3_rst_in <= '0'; end if; if rx3_rst_in = '1' then --and temp_rst = '0' then rx3_rst_internal_ctr <= rx3_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if rx3_rst_internal_ctr = 10 then rx3_rst_in <= '0'; rx3_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; rx3_rst_internal <= reset_reg(5); --------------- Single INIT Register with 0 ---------------------- rx3FDCE_inst5a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx3_rst_in1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx3_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- rx3FDCE_inst6a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx3_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx3_rst_in1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then if rx3_ext_rst = '1' then rx3_int_sig <= '0'; rx3_counter2_g <= (others => '0'); rx3_ms2_g <= '0'; elsif MGT_PLL_LOCK = '1' and rx3_int_sig = '0' then rx3_counter2_g <= rx3_counter2_g + 1; if(rx3_counter2_g < RESET_VALUE) then rx3_ms2_g <= '1'; elsif(rx3_counter2_g = RESET_VALUE) then rx3_ms2_g <= '0'; rx3_counter2_g <= (others => '0'); rx3_int_sig <= '1'; end if; end if; end if; end process; rx3FDCE_instmgta : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => rx3_RESET, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx3_ms2_g -- Data input ); ------------------------------------------------------------------------------------- --RX4 RESET for tile1 process(clk_in) begin if clk_in'event and clk_in = '1' then if rx4_rst_internal = '1' and reset2 = '0' then rx4_rst_in <= '1'; rx4_rst_internal_ctr <=(others => '0'); elsif reset2 = '1' then rx4_rst_in <= '0'; end if; if rx4_rst_in = '1' then --and temp_rst = '0' then rx4_rst_internal_ctr <= rx4_rst_internal_ctr + '1' ; -- ext_rst_in <= '1'; if rx4_rst_internal_ctr = 10 then rx4_rst_in <= '0'; rx4_rst_internal_ctr <=(others => '0'); end if; end if; end if; end process; rx4_rst_internal <= reset_reg(6); --------------- Single INIT Register with 0 ---------------------- rx4FDCE_inst5a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx4_rst_in1, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx4_rst_in -- Data input ); ------------- Single INIT Register with 0 ---------------------- rx4FDCE_inst6a : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') -- INIT => '1') -- Initial value of register ('0' or '1') port map ( Q => rx4_ext_rst, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx4_rst_in1 -- Data input ); ---------------------------------------------------------------- -- 16-bit counter1 - UP COUNTER -------------------------------- -- and reset pulse generation process(clk_in) begin if(clk_in'event and clk_in = '1') then if rx4_ext_rst = '1' then rx4_int_sig <= '0'; rx4_counter2_g <= (others => '0'); rx4_ms2_g <= '0'; elsif MGT_PLL_LOCK = '1' and rx4_int_sig = '0' then rx4_counter2_g <= rx4_counter2_g + 1; if(rx4_counter2_g < RESET_VALUE) then rx4_ms2_g <= '1'; elsif(rx4_counter2_g = RESET_VALUE) then rx4_ms2_g <= '0'; rx4_counter2_g <= (others => '0'); rx4_int_sig <= '1'; end if; end if; end if; end process; rx4FDCE_instmgta : FDCE generic map ( -- INIT => '0') -- Initial value of register ('0' or '1') INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => rx4_RESET, -- Data output C => clk_in, -- Clock input CE => '1', -- Clock enable input CLR => '0', -- RESET_IN, -- Asynchronous clear input D => rx4_ms2_g -- Data input ); end Behavioral; ----------- end of file : rst_module1.vhd -----------------------