-- Project name : Xeon1-D:/Testing_codes/AgFo/TestBench_SYSMON/Sysmon_01/Sysmon_01.ise -- File name : sysmon_01.vhd ---------------------------------------------------------------------------------- -- Company: Raman Research Institute -- Engineer: Deepak Kumar -- -- Create Date: 16:33:48 05/06/2008 -- Design Name: -- Module Name: sysmon_01 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity sysmon_01 is Port ( mgtck3_n : in STD_LOGIC; mgtck3_p : in STD_LOGIC; -- gc8_n : in STD_LOGIC; -- gc8_p : in STD_LOGIC; -- gc9_n : in STD_LOGIC; -- gc9_p : in STD_LOGIC; --- USB interface An : in std_logic_vector(7 downto 0); Dn : inout std_logic_vector(7 downto 0); WR : in std_logic; RD : in std_logic; led1 : out STD_LOGIC; led2 : out STD_LOGIC; led3 : out STD_LOGIC; led4 : out STD_LOGIC; led5 : out STD_LOGIC; led6 : out STD_LOGIC; led7 : out STD_LOGIC; led8 : out STD_LOGIC; led9 : out STD_LOGIC; led10 : out STD_LOGIC; led11 : out STD_LOGIC; led12 : out STD_LOGIC; -- ENOUT : out STD_LOGIC; --DOUT : out STD_LOGIC_VECTOR(9 DOWNTO 0); -- lv1_n : out STD_LOGIC; -- lv1_p : out STD_LOGIC; -- lv2_n : out STD_LOGIC; -- lv2_p : out STD_LOGIC; -- lv3_n : out STD_LOGIC; -- lv3_p : out STD_LOGIC; -- lv4_n : out STD_LOGIC; -- lv4_p : out STD_LOGIC; -- lv5_n : out STD_LOGIC; -- lv5_p : out STD_LOGIC; -- lv6_n : out STD_LOGIC; -- lv6_p : out STD_LOGIC; -- lv7_n : out STD_LOGIC; -- lv7_p : out STD_LOGIC; -- lv8_n : out STD_LOGIC; -- lv8_p : out STD_LOGIC; -- lv9_n : out STD_LOGIC; -- lv9_p : out STD_LOGIC; -- lv10_n : out STD_LOGIC; -- lv10_p : out STD_LOGIC; -- lv11_n : out STD_LOGIC; -- lv11_p : out STD_LOGIC; -- lv12_n : out STD_LOGIC; -- lv12_p : out STD_LOGIC; -- lv65_n : out STD_LOGIC; -- lv65_p : out STD_LOGIC; -- lv38_p : out STD_LOGIC; -- lv39_p : out STD_LOGIC; -- lv40_p : out STD_LOGIC; -- lv41_p : out STD_LOGIC); lv25_p : out STD_LOGIC; lv25_n : out STD_LOGIC; lv26_p : out STD_LOGIC; lv26_n : out STD_LOGIC; lv27_p : out STD_LOGIC; lv27_n : out STD_LOGIC; lv28_p : out STD_LOGIC; lv28_n : out STD_LOGIC; lv29_p : out STD_LOGIC; lv29_n : out STD_LOGIC; lv30_p : out STD_LOGIC; lv30_n : out STD_LOGIC; lv31_p : out STD_LOGIC; lv31_n : out STD_LOGIC; lv32_p : out STD_LOGIC; lv32_n : out STD_LOGIC; lv33_p : out STD_LOGIC; lv33_n : out STD_LOGIC; lv34_p : out STD_LOGIC; lv34_n : out STD_LOGIC ); end sysmon_01; architecture Behavioral of sysmon_01 is signal WRCLK_sig,WRCLK1_sig,RDCLK_sig,RDCLK,WRCLK : std_logic; signal led_cnt : std_logic_vector(31 downto 0); -- sysmon interface signals signal BUSY,DRDY,EOS : std_logic; signal ALM : std_logic_vector(2 downto 0); signal CHANNEL : std_logic_vector(4 downto 0); signal DADDR : std_logic_vector(6 downto 0); signal DO : std_logic_vector(15 downto 0); -- usb interface signals signal POL_SELECTION,PIPELINE_EN,WALSH_WREN_out,usb_load : std_logic; signal GAIN_WREN1_out,GAIN_WREN2_out,CHSEL_WREN_out,OPREG_LOAD_out : std_logic; signal SER_WREN_out,SER_OPREG_LOAD,SCTN_WREN_out,SCTN_OPREG_LOAD : std_logic; signal EXTRST_WR_EN,RST_OPREG_LOAD,OPREG_RDEN : std_logic; signal chip_sel : std_logic_vector(1 downto 0); signal read_reg,usb_command : std_logic_vector(31 downto 0); -- rst module signals signal ms6a_out,rst : std_logic; -- usb interface module component usb_agfo1 Port ( CLK : in std_logic; RESET_IN : IN STD_LOGIC; U_WR_usb : IN STD_LOGIC; U_RD_usb : IN STD_LOGIC; U_ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CHIP_SEL : IN STD_LOGIC_VECTOR(1 downto 0); U_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); READ_REG : IN STD_LOGIC_VECTOR(31 DOWNTO 0); POL_SELECTION : OUT STD_LOGIC; PIPELINE_EN : OUT STD_LOGIC; OUTPUT_REG : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); WALSH_WREN_out : OUT STD_LOGIC; WALSH_OPREG_LOAD : OUT STD_LOGIC; GAIN_WREN1_out : OUT STD_LOGIC; GAIN_WREN2_out : OUT STD_LOGIC; CHSEL_WREN_out : OUT STD_LOGIC; OPREG_LOAD_out : OUT STD_LOGIC; SER_WREN_out : OUT STD_LOGIC; SER_OPREG_LOAD : OUT STD_LOGIC; SCTN_WREN_out : OUT STD_LOGIC; SCTN_OPREG_LOAD : OUT STD_LOGIC; EXTRST_WR_EN : OUT STD_LOGIC; RST_OPREG_LOAD : OUT STD_LOGIC; OPREG_RDEN : OUT STD_LOGIC ); end component; -- reset module component rst_module1 Port ( clk_in : in STD_LOGIC; ext_rst_in : in std_logic; -- counter_out : out std_logic_vector(15 downto 0); ms6a_out : out std_logic; reset_out : out std_logic); end component; begin ---------------------------------------------- DCM_BASE_inst : DCM_BASE generic map ( CLKDV_DIVIDE => 3.0, --7.0,to improve acqisition properly modified on 02222008 7.5, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 6.0, -- Specify period of input clock in ns from 1.25 to 1000.00 CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "HIGH", -- LOW or HIGH frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "HIGH", -- LOW, HIGH, or HIGH_SER frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE port map ( CLK0 => WRCLK1_sig, -- 0 degree DCM CLK ouptput CLK180 => OPEN, -- 180 degree DCM CLK output CLK270 => OPEN, -- 270 degree DCM CLK output CLK2X => OPEN, -- 2X DCM CLK output CLK2X180 => OPEN, -- 2X, 180 degree DCM CLK out CLK90 => OPEN, -- 90 degree DCM CLK output CLKDV => RDCLK, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => OPEN, -- DCM CLK synthesis out (M/D) CLKFX180 => OPEN, -- 180 degree CLK synthesis out LOCKED => OPEN, -- DCM LOCK status output CLKFB => RDCLK_sig, -- DCM clock feedback CLKIN => WRCLK_sig, -- Clock input (from IBUFG, BUFG or DCM) RST => '0' --RST -- DCM asynchronous reset input ); rstm : rst_module1 port map( clk_in => WRCLK, ext_rst_in => '0', ms6a_out => ms6a_out, reset_out => rst ); clk165 : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => true, IBUF_DELAY_VALUE => "0", IOSTANDARD => "LVDS_25") port map ( O => WRCLK_sig, -- Clock buffer output I => mgtck3_p, -- Diff_p clock buffer input IB => mgtck3_n-- Diff_n clock buffer input ); --sctn_se : IBUFGDS -- generic map ( -- CAPACITANCE => "DONT_CARE", -- DIFF_TERM => true, -- IBUF_DELAY_VALUE => "0", -- IOSTANDARD => "LVDS_25") -- port map ( -- O => SCTN, -- Clock buffer output -- I => gc9_p, -- Diff_p clock buffer input -- IB => gc9_n-- Diff_n clock buffer input -- ); -- rdclk_latch : BUFG port map ( O => RDCLK_sig, -- Clock buffer output I => WRCLK1_sig -- Clock buffer input ); WRCLK <= RDCLK_sig; chip_sel <= "00"; -- rdclk_latch : BUFG -- port map ( -- O => WRCLK1, -- Clock buffer output -- I => WRCLK_sig -- Clock buffer input -- ); --sctn_inst:process(WRCLK1) --begin -- if WRCLK1'event and WRCLK1 = '1' then -- SCTN_L1 <= SCTN; -- end if; --end process; ------------------ LED's Display -------------------- led : process(WRCLK) begin if WRCLK'event and WRCLK='1' then led_cnt <= led_cnt + 1; end if; end process led; led1 <= led_cnt(31); led2 <= led_cnt(30); led3 <= led_cnt(29); led4 <= led_cnt(28); led5 <= led_cnt(27); led6 <= led_cnt(26); led7 <= led_cnt(25); led8 <= led_cnt(24); led9 <= led_cnt(23); led10 <= led_cnt(22); led11 <= led_cnt(21); led12 <= led_cnt(20); ----------------------------------------------------------- usb_if_inst1 : usb_agfo1 Port map( CLK => RDCLK, RESET_IN => rst, U_WR_usb => WR, U_RD_usb => RD, U_ADDR => An, CHIP_SEL => chip_sel, U_DATA => Dn, READ_REG => read_reg, POL_SELECTION => POL_SELECTION, PIPELINE_EN => PIPELINE_EN, OUTPUT_REG => usb_command, WALSH_WREN_out => WALSH_WREN_out, WALSH_OPREG_LOAD => usb_load, GAIN_WREN1_out => GAIN_WREN1_out, GAIN_WREN2_out => GAIN_WREN2_out, CHSEL_WREN_out => CHSEL_WREN_out, OPREG_LOAD_out => OPREG_LOAD_out, SER_WREN_out => SER_WREN_out, SER_OPREG_LOAD => SER_OPREG_LOAD, SCTN_WREN_out => SCTN_WREN_out, SCTN_OPREG_LOAD => SCTN_OPREG_LOAD, EXTRST_WR_EN => EXTRST_WR_EN, RST_OPREG_LOAD => RST_OPREG_LOAD, OPREG_RDEN => OPREG_RDEN ); ----------------------------------------------------------------- SYSMON_inst : SYSMON generic map ( INIT_40 => X"1000", -- Configuration register 0 INIT_41 => X"203D", -- Configuration register 1 INIT_42 => X"0A00", -- Configuration register 2 INIT_43 => X"0000", -- Test register 0 INIT_44 => X"0000", -- Test register 1 INIT_45 => X"0000", -- Test register 2 INIT_46 => X"0000", -- Test register 3 INIT_47 => X"0000", -- Test register 4 INIT_48 => X"0101", -- Sequence register 0 INIT_49 => X"0000", -- Sequence register 1 INIT_4A => X"0100", -- Sequence register 2 INIT_4B => X"0000", -- Sequence register 3 INIT_4C => X"0000", -- Sequence register 4 INIT_4D => X"0000", -- Sequence register 5 INIT_4E => X"0000", -- Sequence register 6 INIT_4F => X"0000", -- Sequence register 7 INIT_50 => X"FEB9", -- Alarm limit register 0 INIT_51 => X"0000", -- Alarm limit register 1 INIT_52 => X"0000", -- Alarm limit register 2 INIT_53 => X"0000", -- Alarm limit register 3 INIT_54 => X"FE2A", -- Alarm limit register 4 INIT_55 => X"0000", -- Alarm limit register 5 INIT_56 => X"0000", -- Alarm limit register 6 INIT_57 => X"0000", -- Alarm limit register 7 SIM_MONITOR_FILE => "design.txt") -- Simulation analog entry file port map ( ALM => ALM, -- 3-bit output for temp, Vccint and Vccaux BUSY => BUSY, -- 1-bit output ADC busy signal CHANNEL => CHANNEL, -- 5-bit output channel selection DO => DO, -- 16-bit output data bus for dynamic reconfig DRDY => DRDY, -- 1-bit output data ready for dynamic reconfig -- EOC => EOC, -- 1-bit output end of conversion EOS => EOS, -- 1-bit output end of sequence -- JTAGBUSY => JTAGBUSY, -- 1-bit output JTAG DRP busy -- JTAGLOCKED => JTAGLOCKED, -- 1-bit output DRP port lock -- JTAGMODIFIED => JTAGMODIFIED, -- 1-bit output JTAG write to DRP -- OT => OT, -- 1-bit output over temperature alarm CONVST => '0',--CONVST, -- 1-bit input convert start CONVSTCLK => '0',--CONVSTCLK, -- 1-bit input convert start clock DADDR => DADDR, -- 7-bit input address bus for dynamic reconfig DCLK => RDCLK, -- 1-bit input clock for dynamic reconfig DEN => EOS,--DEN, -- 1-bit input enable for dynamic reconfig DI => "0000000000000000",--DI, -- 16-bit input data bus for dynamic reconfig DWE => '0',--DWE, -- 1-bit input write enable for dynamic reconfig RESET => '0',--RESET, -- 1-bit input active high reset VAUXN => "0000000000000000",--VAUXN, -- 16-bit input N-side auxiliary analog input VAUXP => "0000000000000000",--VAUXP, -- 16-bit input P-side auxiliary analog input VN => '0',--VN, -- 1-bit input N-side analog input VP => '0'--VP) -- 1-bit input P-side analog input ); DADDR <= "00" & CHANNEL; read_reg <= "0000000000000000" & DO; -- cross check manually OBUF_inst1 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv25_p, -- Buffer output (connect directly to top-level port) I => DO(15) -- Buffer input ); OBUF_inst2 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv25_n, -- Buffer output (connect directly to top-level port) I => DO(14) -- Buffer input ); OBUF_inst3 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv26_p, -- Buffer output (connect directly to top-level port) I => DO(13) -- Buffer input ); OBUF_inst4 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv26_n, -- Buffer output (connect directly to top-level port) I => DO(12) -- Buffer input ); OBUF_inst5 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv27_p, -- Buffer output (connect directly to top-level port) I => DO(11) -- Buffer input ); OBUF_inst6 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv27_n, -- Buffer output (connect directly to top-level port) I => DO(10) -- Buffer input ); OBUF_inst7 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv28_p, -- Buffer output (connect directly to top-level port) I => DO(9) -- Buffer input ); OBUF_inst8 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv28_n, -- Buffer output (connect directly to top-level port) I => DO(8) -- Buffer input ); OBUF_inst9 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv29_p, -- Buffer output (connect directly to top-level port) I => DO(7) -- Buffer input ); OBUF_inst10 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv29_n, -- Buffer output (connect directly to top-level port) I => DO(6) -- Buffer input ); OBUF_inst11 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv30_p, -- Buffer output (connect directly to top-level port) I => DO(5) -- Buffer input ); OBUF_inst12 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv30_n, -- Buffer output (connect directly to top-level port) I => CHANNEL(4) -- Buffer input ); OBUF_inst13 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv31_p, -- Buffer output (connect directly to top-level port) I => CHANNEL(3) -- Buffer input ); OBUF_inst14 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv31_n, -- Buffer output (connect directly to top-level port) I => CHANNEL(2) -- Buffer input ); OBUF_inst15 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv32_p, -- Buffer output (connect directly to top-level port) I => CHANNEL(1) -- Buffer input ); OBUF_inst16 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv32_n, -- Buffer output (connect directly to top-level port) I => CHANNEL(0) -- Buffer input ); OBUF_inst17 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv33_p, -- Buffer output (connect directly to top-level port) I => DRDY -- Buffer input ); OBUF_inst18 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv33_n, -- Buffer output (connect directly to top-level port) I => BUSY -- Buffer input ); OBUF_inst19 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv34_p, -- Buffer output (connect directly to top-level port) I => RDCLK -- Buffer input ); OBUF_inst20 : OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map ( O => lv34_n, -- Buffer output (connect directly to top-level port) I => EOS -- Buffer input ); end Behavioral;