-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:54:41 05/09/2008 -- Design Name: sysmon_01_lx -- Module Name: D:/Testing_codes/AgFo/TestBench_SYSMON/sysmon_01_lx/sysmon_01_lx_tb.vhd -- Project Name: sysmon_01_lx -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: sysmon_01_lx -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY sysmon_01_lx_tb_vhd IS END sysmon_01_lx_tb_vhd; ARCHITECTURE behavior OF sysmon_01_lx_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT sysmon_01_lx PORT( mgtck3_n : IN std_logic; mgtck3_p : IN std_logic; An : IN std_logic_vector(7 downto 0); WR : IN std_logic; RD : IN std_logic; Dn : INOUT std_logic_vector(7 downto 0); led1 : OUT std_logic; led2 : OUT std_logic; led3 : OUT std_logic; led4 : OUT std_logic; led5 : OUT std_logic; led6 : OUT std_logic; led7 : OUT std_logic; led8 : OUT std_logic; led9 : OUT std_logic; led10 : OUT std_logic; led11 : OUT std_logic; led12 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL mgtck3_n : std_logic := '0'; SIGNAL mgtck3_p : std_logic := '0'; SIGNAL WR : std_logic := '0'; SIGNAL RD : std_logic := '0'; SIGNAL An : std_logic_vector(7 downto 0) := (others=>'0'); --BiDirs SIGNAL Dn : std_logic_vector(7 downto 0); --Outputs SIGNAL led1 : std_logic; SIGNAL led2 : std_logic; SIGNAL led3 : std_logic; SIGNAL led4 : std_logic; SIGNAL led5 : std_logic; SIGNAL led6 : std_logic; SIGNAL led7 : std_logic; SIGNAL led8 : std_logic; SIGNAL led9 : std_logic; SIGNAL led10 : std_logic; SIGNAL led11 : std_logic; SIGNAL led12 : std_logic; ----------------------------------------------------------------- SIGNAL clk_330MHz,clk165 : std_logic; SIGNAL ctr_330 : std_logic_vector(2 downto 0):=(others => '0'); SIGNAL sctn_counter1 : std_logic_vector(23 downto 0):=(others => '0'); signal TRIGGER : std_logic; SIGNAL INC_RD_CTR,read_done,start_reading : STD_LOGIC:='0'; SIGNAL RD_CTR : STD_LOGIC_VECTOR( 8 DOWNTO 0):=(OTHERS => '0'); --SIGNAL dirname: STRING(1 to 49) := "F:\MWA\ADFB\FIRMWARE\matlab\ADC_OUTPUT\short_sine"; --Input filenames --SIGNAL ninfile1: STRING(1 to 11) := "hr0_dec.txt"; --SIGNAL ninfile2: STRING(1 to 11) := "hr1_dec.txt"; -- SIGNAL ninfile3: STRING(1 to 7) := "hr2.txt"; -- SIGNAL ninfile4: STRING(1 to 7) := "hr3.txt"; ----------------------------------------------------------------- --FOR USB MODULE SIGNAL USB_CLK,USB_CLK1,enable,RESET,USB_CLK_EN : STD_LOGIC; --:='0'; SIGNAL t1_uaddr : std_logic_vector(1 downto 0); SIGNAL t2_uaddr : std_logic := '0'; SIGNAL t3_uaddr : std_logic_vector(4 downto 0):=(OTHERS => '0'); SIGNAL counter : std_logic_vector(15 downto 0):=(OTHERS => '0'); SIGNAL st : std_logic_vector(4 downto 0):=(OTHERS => '0'); SIGNAL COMMAND : std_logic_vector(4 downto 0); SIGNAL DATA: std_logic_vector(7 downto 0); SIGNAL inc_st,resetst,RST_CTR,INC_STATE1,LOAD_DATA,INC_CH_CTR,chsel_done: std_logic := '0'; SIGNAL START_COUNTER,START_COUNTER1,START_DONE,INC_GAIN_CTR,POL1_DONE,POL2_DONE: std_logic := '0'; SIGNAL INT_STATE_CTR ,INT_STATE_CTR1: STD_LOGIC_VECTOR( 3 DOWNTO 0):=(OTHERS => '0'); SIGNAL GAIN_CTR : STD_LOGIC_VECTOR(8 DOWNTO 0):=(OTHERS => '0'); SIGNAL READ_DATA1,READ_DATA2,READ_DATA : STD_LOGIC_VECTOR( 31 DOWNTO 0):=(OTHERS => '0'); SIGNAL STATE_CTR1 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (OTHERS => '0'); SIGNAL CH_CTR : STD_LOGIC_VECTOR(5 DOWNTO 0):=(OTHERS => '0'); SIGNAL CH_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):=(OTHERS => '0'); SIGNAL DONE1,DONE2,DONE3,USB_OP_COMPLETE,USB_OP_COMPLETE1: STD_LOGIC:='0'; -- SIGNAL DC_P_int,DD_P_int : std_logic_vector(7 downto 0); -- SIGNAL temp1,temp2,temp3 : std_logic_vector(1 downto 0); ----------------------------------------------------------------- BEGIN -- Instantiate the Unit Under Test (UUT) uut: sysmon_01_lx PORT MAP( mgtck3_n => mgtck3_n, mgtck3_p => mgtck3_p, An => An, Dn => Dn, WR => WR, RD => RD, led1 => led1, led2 => led2, led3 => led3, led4 => led4, led5 => led5, led6 => led6, led7 => led7, led8 => led8, led9 => led9, led10 => led10, led11 => led11, led12 => led12 ); ----------------------------------------------------------------- clk_330: process -- Generate clock waveform of 330 MHz begin clk_330MHz<= '1', '0' after 1.5 ns, '1' after 3 ns, '0' after 4.5 ns; wait for 6 ns ; end process clk_330; clk_165: process -- Generate clock waveform of 330 MHz begin clk165<= '1', '0' after 4 ns, '1' after 8 ns, '0' after 12 ns; wait for 16 ns ; end process clk_165; --process(clk_330MHz) -- Generate clock waveform of 165 MHz -- begin -- if clk_330MHz'event and clk_330MHz = '1' then -- ctr_330 <= ctr_330+ '1' ; -- end if; --end process; --clk165 <= gc8_p; --gc8_p <= ctr_330(0); --gc8_n <= not ctr_330(0); --clk165 <= gc8_p; mgtck3_p <= clk165; mgtck3_n <= not clk165; TRIGGER_p: process(clk165) -- generate clock waveform begin if clk165'event and clk165 = '1' then sctn_counter1 <= sctn_counter1 + '1'; TRIGGER <= '1'; if sctn_counter1 = 32767 then --8388608 then -- if sctn_counter1 = 512 then --8388608 then TRIGGER <= '0'; sctn_counter1 <= (others => '0'); end if; end if; end process TRIGGER_p; --gc9_p <= TRIGGER; --gc9_n <= not TRIGGER; ----------------------------------------------------------------- ----------------------------------------------------------------- --RESET <= USB_CLK_EN; ----------------------------------------------------------------- --FOR USB MODULE USB_CLKp: process -- generate clock waveform begin -- USB_CLK1 <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns; -- wait for 400 ns ; USB_CLK1 <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns; wait for 40 ns ; end process USB_CLKp; USB_CLK_EN <= '0' , '1' AFTER 4100 NS; USB_CLK <= USB_CLK1 WHEN USB_CLK_EN = '1' ELSE '0'; --CHIP_SEL <= "00"; t1_uaddr<= "00"; --t2_uaddr<= '0'; t3_uaddr<= COMMAND; --"0001";--"0001";--"0000"; An <= t3_uaddr & t2_uaddr & t1_uaddr; Dn <= DATA; enable <= '0', '1' after 200 ns , '0' after 600 ns; --process(USB_CLK)--,CAPTURE_SCTN) -- this process will perform the test. -- file infile1: TEXT is in "gain1.txt"; -- this is your input file name infile.txt. -- variable buf: line; -- variable A: std_logic_vector (31 downto 0); -- begin -- if USB_CLK'event and USB_CLK = '1' then -- if GAIN_CTR < 128 AND INC_GAIN_CTR = '1' then ---- if ENABLE = '1' THEN -- read_vld (infile1, A); -- READ_DATA1<= A; -- end if; -- end if; --end process ; --process(USB_CLK)--,CAPTURE_SCTN) -- this process will perform the test. -- file infile1: TEXT is in "gain2.txt"; -- this is your input file name infile.txt. -- variable buf: line; -- variable B: std_logic_vector (31 downto 0); -- begin -- if USB_CLK'event and USB_CLK = '1' then -- IF GAIN_CTR > 127 AND GAIN_CTR < 256 THEN -- if LOAD_DATA= '1' AND INC_GAIN_CTR = '1' then -- read_vld (infile1, B); -- READ_DATA2 <= B; -- end if; -- END IF; -- end if; --end process ; --process(USB_CLK)--,CAPTURE_SCTN) -- this process will perform the test. -- file infile1: TEXT is in "usb_ip.txt"; -- this is your input file name infile.txt. -- variable buf: line; -- variable C: std_logic_vector (31 downto 0); -- begin -- if USB_CLK'event and USB_CLK = '1' then -- if INC_CH_CTR = '1' and CH_CTR < 34 then -- read_vld (infile1, C); -- CH_DATA <= C; -- end if; -- end if; --end process ; --=============================================================== process(clk_330MHz) begin if clk_330MHz'event and clk_330MHz = '1' then IF clk165 = '1' THEN USB_OP_COMPLETE1 <= USB_OP_COMPLETE; END IF; end if; end process; ----------------------------------------------------------------- ------ Reading from the file for serial_pol-1 data ---------------- --ser_p1_process: --process(clk_330MHz)--,CAPTURE_SCTN) -- this process will perform the test. ---- file infile0: TEXT is in dirname & ninfile1; -- this is your input file name infile.txt. --file infile0: TEXT is in "ser_data_p1.txt"; -- this is your input file name infile.txt. --variable buf: line; --variable CHECK0: std_logic_vector (1 downto 0); --begin -- if clk_330MHz'event and clk_330MHz = '1' then -- if USB_OP_COMPLETE1 = '1' then -- read_vld (infile0, CHECK0); -- fda1_p <= CHECK0(0); -- end if; -- end if; --end process ser_p1_process; --fda1_n <= NOT fda1_p; --------------------------------------------- ------ Pol-1 data to all the remaining inputs --fda2_p <= fda1_p; --fda2_n <= NOT fda2_p; --fda3_p <= fda1_p; --fda3_n <= NOT fda3_p; --fda4_p <= fda1_p; --fda4_n <= NOT fda4_p; --fda5_p <= fda1_p; --fda5_n <= NOT fda5_p; --fda6_p <= fda1_p; --fda6_n <= NOT fda6_p; --fds7_p <= fda1_p; --fds7_n <= NOT fds7_p; --fda8_p <= fda1_p; --fda8_n <= NOT fda8_p; -- ----=============================================================== ------ Reading from the file for serial_pol-2 data ---------------- --ser_p2_process: --process(clk_330MHz)--,CAPTURE_SCTN) -- this process will perform the test. --file infile0: TEXT is in "ser_data_p2.txt"; -- this is your input file name infile.txt. --variable buf: line; --variable CHECK1 : std_logic_vector (1 downto 0); --begin -- if clk_330MHz'event and clk_330MHz = '1' then -- if USB_OP_COMPLETE1 = '1' then -- read_vld (infile0, CHECK1); -- fdb1_p <= CHECK1(0); -- end if; -- end if; --end process ser_p2_process; --fdb1_n <= NOT fdb1_p; --------------------------------------------- ------ Pol-2 data to all the remaining inputs --fds2_p <= fdb1_p; --fds2_n <= NOT fds2_p; --fdb3_p <= fdb1_p; --fdb3_n <= NOT fdb3_p; --fdb4_p <= fdb1_p; --fdb4_n <= NOT fdb4_p; --fdb5_p <= fdb1_p; --fdb5_n <= NOT fdb5_p; --fdb6_p <= fdb1_p; --fdb6_n <= NOT fdb6_p; --fdb7_p <= fdb1_p; --fdb7_n <= NOT fdb7_p; --fdb8_p <= fdb1_p; --fdb8_n <= NOT fdb8_p; ----=============================================================== ------ Reading from the file for serial_clock ---- ---------------- --ser_clk_process: --process(clk_330MHz)--,CAPTURE_SCTN) -- this process will perform the test. --file infile0: TEXT is in "ser_clk.txt"; -- this is your input file name infile.txt. --variable buf: line; --variable CHECK2 : std_logic_vector (1 downto 0); --begin -- if clk_330MHz'event and clk_330MHz = '1' then -- if USB_OP_COMPLETE1 = '1' then -- read_vld (infile0, CHECK2); -- fds1_p <= not CHECK2(0); -- end if; -- end if; --end process ser_clk_process; --fds1_n <= NOT fds1_p; --------------------------------------------- ------ Clock data to all the remaining inputs --fdb2_p <= fds1_p; --fdb2_n <= NOT fdb2_p; --fds3_p <= fds1_p; --fds3_n <= NOT fds3_p; --fck4_p <= fds1_p; --fck4_n <= NOT fck4_p; --fck5_p <= fds1_p; --fck5_n <= NOT fck5_p; --fds6_p <= fds1_p; --fds6_n <= NOT fds6_p; --fda7_p <= fds1_p; --fda7_n <= NOT fda7_p; --fck8_p <= fds1_p; --fck8_n <= NOT fck8_p; ----=============================================================== --WRITING THE SERIALISER TO OUTPUT FILE --write1_process1: -- process(clk_330MHz) -- this process will perform the test. -- file outfile0: TEXT is out "P1_CLK.txt"; -- this is your output file name. -- begin -- if clk_330MHz = '1' and clk_330MHz'event then -- write_vld(outfile0,temp1); -- end if; -- end process write1_process1; -- --temp1 <= '0' & LRJP0; -- --write1_process2: -- process(clk_330MHz) -- this process will perform the test. -- file outfile1: TEXT is out "P1_DATA.txt"; -- this is your output file name. -- begin -- if clk_330MHz'event and clk_330MHz = '1' then -- write_vld(outfile1,temp2); -- end if; -- end process write1_process2; --temp2 <= '0' & LRJP1; -- -- --write1_process3: -- process(clk_330MHz) -- this process will perform the test. -- file outfile1: TEXT is out "P2_DATA.txt"; -- this is your output file name. -- begin -- if clk_330MHz'event and clk_330MHz = '1' then -- write_vld(outfile1,temp3); -- end if; -- end process write1_process3; --temp3 <= '0' & LRJP2; -- -- --=============================================================== process(RESET,USB_CLK) begin if USB_CLK'event and USB_CLK = '1' then if RESET = '0' then st <= (others => '0'); elsif inc_st = '1' then st <= st + '1'; end if; end if; end process; PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF RESET = '0' THEN COMMAND <= (OTHERS=>'0'); WR <= '0'; START_COUNTER <= '0'; INC_GAIN_CTR <= '0'; POL1_DONE <= '0'; POL2_DONE <= '0'; t2_uaddr<= '0'; resetst <= '0'; inc_st<= '0'; RST_CTR<= '0'; START_COUNTER1 <= '0'; LOAD_DATA <= '0'; chsel_done <= '0'; DONE1 <= '0'; DONE2 <= '0'; DONE3 <= '0'; USB_OP_COMPLETE <= '0'; ELSE CASE st IS WHEN "00000" => COMMAND <= "00000"; WR <= '0'; inc_st <= '1'; WHEN "00001" => WR <= '1'; inc_st <= '1'; WHEN "00010" => WR <= '1'; inc_st <= '1'; WHEN "00011" => WR <= '1'; inc_st <= '1'; WHEN "00100" => WR <= '1'; inc_st <= '1'; WHEN "00101" => WR <= '0'; inc_st <= '0'; START_COUNTER <= '1'; WHEN "00110" => IF INT_STATE_CTR = 0 THEN COMMAND <= "00110"; DATA <= (OTHERS => '0'); WR <= '1'; inc_st <= '0'; START_COUNTER <= '1'; ELSIF INT_STATE_CTR = 1 THEN COMMAND <= "00110"; DATA <= (OTHERS => '0'); WR <= '0'; START_COUNTER <= '1'; ELSIF INT_STATE_CTR = 2 THEN DATA <= X"01"; WR <= '1'; ELSIF INT_STATE_CTR = 3 THEN DATA <= X"01"; WR <= '0'; ELSIF INT_STATE_CTR = 4 THEN DATA <= X"00"; WR <= '1'; ELSIF INT_STATE_CTR = 5 THEN DATA <= X"00"; WR <= '0'; ELSIF INT_STATE_CTR = 6 THEN DATA <= X"C0";--X"00"; --X"FF"; WR <= '1'; ELSIF INT_STATE_CTR = 7 THEN DATA <= X"C0";--X"00"; --X"FF"; WR <= '0'; ELSIF INT_STATE_CTR = 8 THEN DATA <= X"C3";--X"00"; --X"FF"; WR <= '1'; START_COUNTER <= '0'; ELSIF INT_STATE_CTR = 9 THEN DATA <= X"C3";--X"00"; --X"FF"; WR <= '0'; START_COUNTER <= '0'; inc_st <= '1'; --st <= (others => '0'); t2_uaddr<= '0'; USB_OP_COMPLETE <= '1'; END IF; -- WHEN "00111" => -- IF t2_uaddr = '0' AND POL1_DONE = '0' then -- READ_DATA <= READ_DATA1; -- ELSIF t2_uaddr = '1' AND POL1_DONE = '1' then -- READ_DATA <= READ_DATA2; -- END IF; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00010"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= READ_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00010"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_GAIN_CTR <= '1'; -- DATA <= READ_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND POL2_DONE = '0' THEN -- START_COUNTER1<= '1'; -- -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= READ_DATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_GAIN_CTR <= '0'; ---- START_COUNTER1<= '1'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= READ_DATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= READ_DATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=READ_DATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= READ_DATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= READ_DATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= READ_DATA(31 downto 24); -- WR <= '1'; -- INC_GAIN_CTR <= '1'; -- IF GAIN_CTR = 256 THEN -- RST_CTR <= '1'; -- END IF; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= READ_DATA(31 downto 24); -- WR <= '0'; -- INC_GAIN_CTR <= '0'; -- START_COUNTER1 <= '0'; -- IF GAIN_CTR = 128 THEN -- t2_uaddr<= '1'; -- END IF; -- IF GAIN_CTR = 128 THEN -- POL1_DONE <= '1'; -- END IF; -- -- IF GAIN_CTR = 127 THEN -- LOAD_DATA <= '1'; -- END IF; -- -- -- IF GAIN_CTR = 256 THEN -- INC_GAIN_CTR <= '0'; -- START_COUNTER1<= '0'; -- POL2_DONE <= '1'; -- inc_st <= '1'; -- t2_uaddr<= '0'; -- RST_CTR <= '0'; -- ---- ELSE ---- inc_st <= '0'; -- END IF; -- END IF; -- END IF; -- -- WHEN "01000" => -- inc_st <= '0'; -- -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00011"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= CH_DATA(7 downto 0); -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00011"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- INC_CH_CTR <= '1'; -- DATA <= CH_DATA(7 downto 0); -- -- ELSIF STATE_CTR1 = 2 AND chsel_done = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= CH_DATA(7 downto 0); -- WR <= '1'; -- INC_STATE1 <= '0'; -- INC_CH_CTR <= '0'; ---- START_COUNTER1<= '1'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= CH_DATA(7 downto 0); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= CH_DATA(15 downto 8); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <=CH_DATA(15 downto 8); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= CH_DATA(23 downto 16); -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= CH_DATA(23 downto 16); -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= CH_DATA(31 downto 24); -- WR <= '1'; -- INC_CH_CTR <= '1'; -- IF CH_CTR = 33 THEN -- RST_CTR <= '1'; -- -- END IF; -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= CH_DATA(31 downto 24); -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- -- IF CH_CTR = 33 THEN -- t2_uaddr<= '1'; -- INC_CH_CTR <= '0'; -- START_COUNTER1<= '0'; -- inc_st <= '1'; -- chsel_done <= '1'; -- RST_CTR <= '0'; -- -- END IF; -- END IF; -- END IF; -- WHEN "01001" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00100"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"02"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00100"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"02"; -- -- ELSIF STATE_CTR1 = 2 AND DONE1 = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"02"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"02"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"02"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"02"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- START_COUNTER1 <= '0'; -- DONE1 <= '1'; -- RST_CTR <= '0'; -- inc_st <= '1'; -- -- -- END IF; -- END IF; -- -- WHEN "01010" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00101"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"00"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00101"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"00"; -- -- ELSIF STATE_CTR1 = 2 AND DONE2 = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"00"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- RST_CTR <= '0'; -- DONE2 <= '1'; -- inc_st <= '1'; -- -- END IF; -- END IF; -- WHEN "01011" => -- IF STATE_CTR1 = 0 THEN -- WR <= '1'; -- COMMAND <= "00110"; -- inc_st <= '0'; -- INC_STATE1 <= '1'; -- DATA <= X"00"; -- START_COUNTER1<= '0'; -- -- -- ELSIF STATE_CTR1 = 1 THEN -- COMMAND <= "00110"; -- WR <= '0'; -- INC_STATE1 <= '0'; -- DATA <= X"00"; -- -- ELSIF STATE_CTR1 = 2 AND DONE3 = '0' THEN -- START_COUNTER1<= '1'; -- IF INT_STATE_CTR1 = 0 THEN -- DATA <= X"00"; -- WR <= '1'; -- INC_STATE1 <= '0'; -- ELSIF INT_STATE_CTR1 = 1 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 2 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 3 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 4 THEN -- DATA <= X"00"; -- WR <= '1'; -- ELSIF INT_STATE_CTR1 = 5 THEN -- DATA <= X"00"; -- WR <= '0'; -- -- ELSIF INT_STATE_CTR1 = 6 THEN -- DATA <= X"00"; -- WR <= '1'; -- RST_CTR <= '1'; -- -- ELSIF INT_STATE_CTR1 = 7 THEN -- DATA <= X"00"; -- WR <= '0'; -- INC_CH_CTR <= '0'; -- START_COUNTER1 <= '0'; -- RST_CTR <= '0'; -- DONE3 <= '1'; -- inc_st <= '1'; -- USB_OP_COMPLETE <= '1'; -- -- -- END IF; -- END IF; ------------------------------------------------------------------------------------- WHEN "01110" => -- wait_st <= wait_st + '1'; -- if wait_st = 100 then -- start_reading <= '1'; -- end if; IF STATE_CTR1 = 0 THEN WR <= '1'; RD <= '0'; COMMAND <= "01000"; inc_st <= '0'; INC_STATE1 <= '1'; DATA <= (OTHERS => 'Z'); START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "01000"; WR <= '1'; RD <= '0'; INC_STATE1 <= '0'; DATA <= (OTHERS => 'Z'); INC_RD_CTR <= '1'; ELSIF STATE_CTR1 = 2 and start_reading = '0' then --AND read_done = '0' THEN START_COUNTER1<= '1'; IF INT_STATE_CTR1 = 0 THEN DATA <= (OTHERS => 'Z'); RD <= '1'; INC_STATE1 <= '0'; INC_RD_CTR <= '0'; ELSIF INT_STATE_CTR1 = 1 THEN DATA <= (OTHERS => 'Z'); RD <= '0'; ELSIF INT_STATE_CTR1 = 2 THEN DATA <= (OTHERS => 'Z'); RD <= '1'; ELSIF INT_STATE_CTR1 = 3 THEN DATA <= (OTHERS => 'Z'); RD <= '0'; ELSIF INT_STATE_CTR1 = 4 THEN DATA <= (OTHERS => 'Z'); RD <= '1'; ELSIF INT_STATE_CTR1 = 5 THEN DATA <= (OTHERS => 'Z'); RD <= '0'; ELSIF INT_STATE_CTR1 = 6 THEN DATA <= (OTHERS => 'Z'); RD <= '1'; -- INC_RD_CTR <= '1'; -- IF RD_CTR = 255 THEN RST_CTR <= '1'; -- END IF; ELSIF INT_STATE_CTR1 = 7 THEN DATA <= (OTHERS => 'Z'); RD <= '0'; START_COUNTER1 <= '0'; read_done <= '0'; ---- IF RD_CTR = 255 then -- read_done <= '1'; INC_RD_CTR <= '0'; -- START_COUNTER1 <= '0'; RST_CTR <= '0'; -- DONE4 <= '1'; -- inc_st <= '1'; -- END IF; END IF; END IF; ------------------------------------------------------------------------------------- WHEN "00111" => IF STATE_CTR1 = 0 THEN WR <= '1'; COMMAND <= "00000"; inc_st <= '1'; START_COUNTER1<= '0'; ELSIF STATE_CTR1 = 1 THEN COMMAND <= "00000"; WR <= '0'; INC_STATE1 <= '0'; END IF; WHEN OTHERS => WR <= '0'; RD <= '0'; END CASE; END IF; END IF; END PROCESS; PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF START_COUNTER = '1' THEN INT_STATE_CTR <= INT_STATE_CTR + '1'; ELSE INT_STATE_CTR <= INT_STATE_CTR; END IF; IF INT_STATE_CTR = 9 THEN INT_STATE_CTR <= (OTHERS => '0'); END IF; END IF; END PROCESS; -------------------------------------------------------------------------- PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF INC_STATE1 = '1' THEN STATE_CTR1 <= STATE_CTR1 + '1'; ELSE STATE_CTR1 <= STATE_CTR1; END IF; IF RST_CTR = '1' THEN STATE_CTR1 <= (OTHERS => '0'); END IF; END IF; END PROCESS; PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF START_COUNTER1= '1' THEN INT_STATE_CTR1 <= INT_STATE_CTR1 + '1'; ELSE INT_STATE_CTR1 <= INT_STATE_CTR1; END IF; IF INT_STATE_CTR1 = 7 THEN INT_STATE_CTR1 <= (OTHERS => '0'); END IF; END IF; END PROCESS; --------------------------------------------------------- --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_GAIN_CTR = '1' THEN -- GAIN_CTR <= GAIN_CTR + '1'; -- ELSE -- GAIN_CTR <= GAIN_CTR; -- END IF; -- -- IF GAIN_CTR = 257 THEN -- GAIN_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; --PROCESS(USB_CLK,RESET) --BEGIN -- IF USB_CLK'EVENT AND USB_CLK = '1' THEN -- IF INC_CH_CTR = '1' THEN -- CH_CTR <= CH_CTR + '1'; -- ELSE -- CH_CTR <= CH_CTR; -- END IF; -- -- IF CH_CTR = 34 THEN -- CH_CTR <= (OTHERS => '0'); -- END IF; -- -- END IF; --END PROCESS; PROCESS(USB_CLK,RESET) BEGIN IF USB_CLK'EVENT AND USB_CLK = '1' THEN IF INC_RD_CTR = '1' THEN RD_CTR <= RD_CTR + '1'; ELSE RD_CTR <= RD_CTR; END IF; IF RD_CTR = 255 THEN RD_CTR <= (OTHERS => '0'); END IF; END IF; END PROCESS; END; ------------------ end of file : sysmon_01_tb.vhd ----------