--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:31:27 08/13/2009
-- Design Name:   delay_load_PULSE_GEN
-- Module Name:   I:/MWA_DIGITAL_RECEIVER-2009/AGFO/FIBRE_V8_MIT_SX_bkpln/TB_delay.vhd
-- Project Name:  agfo_fibre_V8_SX
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: delay_load_PULSE_GEN
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY TB_delay_vhd IS
END TB_delay_vhd;

ARCHITECTURE behavior OF TB_delay_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT delay_load_PULSE_GEN
	PORT(
		reset_in : IN std_logic;
		clk_in : IN std_logic;
		DELAY_ENABLE : IN std_logic;
		DELAY_LOAD_PULSE : IN std_logic;
		usb_command : IN std_logic_vector(31 downto 0);          
		LOAD_PULSE1 : OUT std_logic;
		LOAD_PULSE2 : OUT std_logic;
		LOAD_PULSE3 : OUT std_logic;
		LOAD_PULSE4 : OUT std_logic;
		LOAD_PULSE5 : OUT std_logic;
		LOAD_PULSE6 : OUT std_logic;
		LOAD_PULSE7 : OUT std_logic;
		LOAD_PULSE8 : OUT std_logic;
		LOAD_PULSE9 : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset_in :  std_logic := '0';
	SIGNAL clk_in :  std_logic := '0';
	SIGNAL DELAY_ENABLE :  std_logic := '0';
	SIGNAL DELAY_LOAD_PULSE :  std_logic := '0';
	SIGNAL usb_command :  std_logic_vector(31 downto 0) := (others=>'0');

	--Outputs
	SIGNAL LOAD_PULSE1 :  std_logic;
	SIGNAL LOAD_PULSE2 :  std_logic;
	SIGNAL LOAD_PULSE3 :  std_logic;
	SIGNAL LOAD_PULSE4 :  std_logic;
	SIGNAL LOAD_PULSE5 :  std_logic;
	SIGNAL LOAD_PULSE6 :  std_logic;
	SIGNAL LOAD_PULSE7 :  std_logic;
	SIGNAL LOAD_PULSE8 :  std_logic;
	SIGNAL LOAD_PULSE9 :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: delay_load_PULSE_GEN PORT MAP(
		reset_in => reset_in,
		clk_in => clk_in,
		DELAY_ENABLE => DELAY_ENABLE,
		DELAY_LOAD_PULSE => DELAY_LOAD_PULSE,
		usb_command => usb_command,
		LOAD_PULSE1 => LOAD_PULSE1,
		LOAD_PULSE2 => LOAD_PULSE2,
		LOAD_PULSE3 => LOAD_PULSE3,
		LOAD_PULSE4 => LOAD_PULSE4,
		LOAD_PULSE5 => LOAD_PULSE5,
		LOAD_PULSE6 => LOAD_PULSE6,
		LOAD_PULSE7 => LOAD_PULSE7,
		LOAD_PULSE8 => LOAD_PULSE8,
		LOAD_PULSE9 => LOAD_PULSE9
	);


clk_33: 
process -- Generate clock waveform of 330 MHz
    begin 
    	clk_in<= '1', '0' after 15  ns, '1' after 30 ns, '0' after   45 ns;
    	wait for 60 ns	; 
end process clk_33; 

reset_in <= '1' , '0'  AFTER 200 NS;

DELAY_ENABLE <= '0', '1' after 210 ns , '0' after 510 ns;
DELAY_LOAD_PULSE <= '0', '1' after 210 ns, '0' after 240 ns, '1' after 270 ns, 
                    '0' after 300 ns, '1' after 330 ns, 
						  '0' after 360 ns, '1' after 390 ns, 
						  '0' after 420 ns, '1' after 450 ns, 
						  '0' after 480 ns, '1' after 510 ns,
						  '0' after 540 ns;




END;