--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:43:43 08/20/2009
-- Design Name:   delay_load_PULSE_GEN_chk
-- Module Name:   I:/MWA_DIGITAL_RECEIVER-2009/AGFO/FIBRE_V6c_MIT_SX_bkpln/tb_delay1.vhd
-- Project Name:  agfo_fibre_V6c_SX
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: delay_load_PULSE_GEN_chk
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_delay1_vhd IS
END tb_delay1_vhd;

ARCHITECTURE behavior OF tb_delay1_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT delay_load_PULSE_GEN_chk
	PORT(
		reset_in : IN std_logic;
		clk_in : IN std_logic;
		clk200 : IN std_logic;
		DELAY_ENABLE : IN std_logic;
		DELAY_LOAD_PULSE : IN std_logic;
		usb_command : IN std_logic_vector(31 downto 0)       
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset_in :  std_logic := '0';
	SIGNAL clk_in :  std_logic := '0';
	SIGNAL clk200 :  std_logic := '0';
	SIGNAL DELAY_ENABLE :  std_logic := '0';
	SIGNAL DELAY_LOAD_PULSE :  std_logic := '0';
	SIGNAL usb_command :  std_logic_vector(31 downto 0) := (others=>'0');

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: delay_load_PULSE_GEN_chk PORT MAP(
		reset_in => reset_in,
		clk_in => clk_in,
		clk200 => clk200,
		DELAY_ENABLE => DELAY_ENABLE,
		DELAY_LOAD_PULSE => DELAY_LOAD_PULSE,
		usb_command => usb_command
	);


clk_33: 
process -- Generate clock waveform of 330 MHz
    begin 
    	clk_in<= '1', '0' after 15  ns, '1' after 30 ns, '0' after   45 ns;
    	wait for 60 ns	; 
end process clk_33; 

clk_200:
process -- Generate clock waveform of 330 MHz
    begin 
    	clk200<= '1', '0' after 2.5  ns, '1' after 5 ns, '0' after   7.5 ns;
    	wait for 10 ns	; 
end process clk_200; 


reset_in <= '1' , '0'  AFTER 200 NS, '1' after 600 ns , '0' after 800 ns;

DELAY_ENABLE <= '0', '1' after 210 ns , '0' after 510 ns,
                     '1' after 810 ns, '0' after 1020 ns;
DELAY_LOAD_PULSE <= '0', '1' after 210 ns, '0' after 240 ns, '1' after 270 ns, 
                    '0' after 300 ns, '1' after 330 ns, 
						  '0' after 360 ns, '1' after 390 ns, 
						  '0' after 420 ns, '1' after 450 ns, 
						  '0' after 480 ns, '1' after 510 ns,
						  '0' after 540 ns, '1' after 810 ns, 
						  '0' after 840 ns, '1' after 870 ns, 
						  '0' after 900 ns, '1' after 930 ns, 
						  '0' after 960 ns, '1' after 990 ns,
						  '0' after 1020 ns;


usb_command <= X"40000080", X"20000000" after 510 ns;





END;