// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
ram1024 YourInstanceName (
.clka(clka),
.dina(dina), // Bus [9 : 0]
.addra(addra), // Bus [9 : 0]
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [9 : 0]
.regceb(regceb),
.doutb(doutb)); // Bus [9 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
fifo1 YourInstanceName (
.din(din), // Bus [159 : 0]
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.dout(dout), // Bus [19 : 0]
.empty(empty),
.full(full),
.rd_data_count(rd_data_count), // Bus [6 : 0]
.wr_data_count(wr_data_count)); // Bus [3 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
ram160 YourInstanceName (
.clka(clka),
.dina(dina), // Bus [159 : 0]
.addra(addra), // Bus [2 : 0]
.ena(ena),
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [3 : 0]
.enb(enb),
.doutb(doutb)); // Bus [79 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
usbrd_dpram YourInstanceName (
.clka(clka),
.dina(dina), // Bus [31 : 0]
.addra(addra), // Bus [4 : 0]
.ena(ena),
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [4 : 0]
.enb(enb),
.doutb(doutb)); // Bus [31 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
usbreadram32 YourInstanceName (
.clka(clka),
.dina(dina), // Bus [31 : 0]
.addra(addra), // Bus [4 : 0]
.ena(ena),
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [4 : 0]
.enb(enb),
.doutb(doutb)); // Bus [31 : 0]
-- The following code must appear in the VHDL architecture header:
component ram1024
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(9 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(9 downto 0);
regceb: IN std_logic;
doutb: OUT std_logic_VECTOR(9 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : ram1024
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
regceb => regceb,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component fifo1
port (
din: IN std_logic_VECTOR(159 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(19 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(6 downto 0);
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : fifo1
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count);
-- The following code must appear in the VHDL architecture header:
component ram160
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(159 downto 0);
addra: IN std_logic_VECTOR(2 downto 0);
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(3 downto 0);
enb: IN std_logic;
doutb: OUT std_logic_VECTOR(79 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : ram160
port map (
clka => clka,
dina => dina,
addra => addra,
ena => ena,
wea => wea,
clkb => clkb,
addrb => addrb,
enb => enb,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component usbrd_dpram
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
addra: IN std_logic_VECTOR(4 downto 0);
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(4 downto 0);
enb: IN std_logic;
doutb: OUT std_logic_VECTOR(31 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : usbrd_dpram
port map (
clka => clka,
dina => dina,
addra => addra,
ena => ena,
wea => wea,
clkb => clkb,
addrb => addrb,
enb => enb,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component usbreadram32
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
addra: IN std_logic_VECTOR(4 downto 0);
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(4 downto 0);
enb: IN std_logic;
doutb: OUT std_logic_VECTOR(31 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : usbreadram32
port map (
clka => clka,
dina => dina,
addra => addra,
ena => ena,
wea => wea,
clkb => clkb,
addrb => addrb,
enb => enb,
doutb => doutb);