---------------------------------------------------------------------------------- -- Company: RAMAN RESEARCH INSTITUTE -- Engineer: -- -- Create Date: 11:50:58 07/19/2008 -- Design Name: -- Module Name: trans_test2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity trans_test2 is Port ( clk_165 : in STD_LOGIC; rst : in STD_LOGIC; sctn_in : in STD_LOGIC; valid_regceb : in STD_LOGIC; valid_enable : in STD_LOGIC; valid_data : in STD_LOGIC_VECTOR (159 downto 0); fout : in STD_LOGIC; TILE0_TXUSRCLK20 : in STD_LOGIC; --clk_125 TILE1_TXUSRCLK20 : in STD_LOGIC; --clk_125 TILE0TX_RST : in STD_LOGIC; TILE1TX_RST : in STD_LOGIC; fibre_no : in STD_LOGIC_VECTOR(2 downto 0); no_ch_fibre1 : in STD_LOGIC_VECTOR(2 downto 0); --0 to 7 chs no_ch_fibre2 : in STD_LOGIC_VECTOR(2 downto 0); --8 to 15 chs no_ch_fibre3 : in STD_LOGIC_VECTOR(2 downto 0); --16 to 23 chs no_ch_fibre4 : in STD_LOGIC_VECTOR(2 downto 0); --24 to 31 chs actual_diag : in STD_LOGIC; node_in : in STD_LOGIC_VECTOR(7 downto 0); ---Outputs dout1 : out STD_LOGIC_VECTOR (15 downto 0); dout2 : out STD_LOGIC_VECTOR (15 downto 0); dout3 : out STD_LOGIC_VECTOR (15 downto 0); dout4 : out STD_LOGIC_VECTOR (15 downto 0); charisk1 : out STD_LOGIC_VECTOR (1 downto 0); charisk2 : out STD_LOGIC_VECTOR (1 downto 0); charisk3 : out STD_LOGIC_VECTOR (1 downto 0); charisk4 : out STD_LOGIC_VECTOR (1 downto 0); txchardispmode1 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval1 : out std_logic_vector (1 downto 0); -- to MGT; txchardispmode2 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval2 : out std_logic_vector (1 downto 0); -- to MGT; txchardispmode3 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval3 : out std_logic_vector (1 downto 0); -- to MGT; txchardispmode4 : out std_logic_vector (1 downto 0); -- to MGT; txchardispval4 : out std_logic_vector (1 downto 0); -- to MGT; ip_dpram_en : out STD_LOGIC; --Monitoring data_load_MON : out STD_LOGIC; valid_enableL1_MON : out STD_LOGIC ---------- ); end trans_test2; architecture trans of trans_test2 is signal counter_regceb,counter_regceb_int,counter_enable,counter_enable_int,valid_enableL1 : std_logic := '0'; signal counter_a : std_logic_vector(5 downto 0); signal valid_dataL1, valid_dataL2,counter_data : std_logic_vector(159 downto 0); signal c1 : std_logic_vector(9 downto 0):=(others => '0'); signal c2 : std_logic_vector(4 downto 0):=(others => '0'); signal data_load, sctn_L1 : std_logic; signal no_ch_fibre_cnt_out : std_logic_vector(2 downto 0); signal start_rd1,start_rd2,start_rd3,start_rd4 : STD_LOGIC; signal wr_en1,wr_en2,wr_en3,wr_en4 : std_logic_vector(0 downto 0); signal addra : std_logic_vector(2 downto 0); signal addrb1,addrb2,addrb3,addrb4 : std_logic_vector(3 downto 0); signal ram_data1,ram_data2,ram_data3,ram_data4 : std_logic_vector(79 downto 0); signal rd_complete,rd_complete1,rd_complete2,rd_complete3,rd_complete4,enb1,enb2,enb3,enb4 : std_logic; signal RST_LATCHED : std_logic; ----Component Declaration----------------------------------------------------------------- ---------Write enable generation--------------------------- component write_en_gen Port ( clk_165 : in STD_LOGIC; --165Mhz clk data_load : in STD_LOGIC; -- latched Valid_receb valid_enable : in STD_LOGIC; -- latched valid enable rst : in STD_LOGIC; fibre_no : in STD_LOGIC_VECTOR(2 downto 0); no_ch_fibre1 : in STD_LOGIC_VECTOR(5 downto 3); no_ch_fibre2 : in STD_LOGIC_VECTOR(8 downto 6); no_ch_fibre3 : in STD_LOGIC_VECTOR(11 downto 9); no_ch_fibre4 : in STD_LOGIC_VECTOR(14 downto 12); rd_complete : in STD_LOGIC; -- from wr_en_gen --outputs addra : out STD_LOGIC_VECTOR(2 downto 0); -- to load_ram wr_en1 : out STD_LOGIC_VECTOR(0 downto 0); -- to load_ram wr_en2 : out STD_LOGIC_VECTOR(0 downto 0); wr_en3 : out STD_LOGIC_VECTOR(0 downto 0); wr_en4 : out STD_LOGIC_VECTOR(0 downto 0); start_rd1 : out STD_LOGIC; -- to packetization start_rd2 : out STD_LOGIC; start_rd3 : out STD_LOGIC; start_rd4 : out STD_LOGIC ); end component; ---------RAM------------------------------------------ component ram160 port ( clka : IN std_logic; dina : IN std_logic_VECTOR(159 downto 0); addra : IN std_logic_VECTOR(2 downto 0); ena : IN std_logic; wea : IN std_logic_VECTOR(0 downto 0); clkb : IN std_logic; addrb : IN std_logic_VECTOR(3 downto 0); enb : IN std_logic; doutb : OUT std_logic_VECTOR(79 downto 0)); end component; ------PACKETIZATION------------------------------------ component packetization Port ( rst : in STD_LOGIC; TX_RST : in STD_LOGIC; clk_125 : in STD_LOGIC; -- read clk 125Mhz clk_165 : in std_logic; sctn_in : in STD_LOGIC; sig : in STD_LOGIC_VECTOR (1 downto 0); -- fibre no start_rd : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (79 downto 0); -- read data from RAM fibre_no : in STD_LOGIC_VECTOR(2 downto 0); no_ch_fibre1 : in STD_LOGIC_VECTOR(2 downto 0); --0 to 7 chs no_ch_fibre2 : in STD_LOGIC_VECTOR(2 downto 0); --8 to 15 chs no_ch_fibre3 : in STD_LOGIC_VECTOR(2 downto 0); --16 to 23 chs no_ch_fibre4 : in STD_LOGIC_VECTOR(2 downto 0); --24 to 31 chs node_in : in STD_LOGIC_VECTOR(7 downto 0); --outputs addrb : out STD_LOGIC_VECTOR(3 downto 0); -- add to ram -- enb : out STD_LOGIC; -- read en to ram rd_complete : out STD_LOGIC; dout : out STD_LOGIC_VECTOR (15 downto 0); charisk : out std_logic_vector (1 downto 0); -- to MGT txchardispmode: out std_logic_vector (1 downto 0); -- to MGT txchardispval: out std_logic_vector (1 downto 0) -- to MGT ); end component; --------------------------------------------------------------------------------- begin --Latching i/p data, regceb and sctn--------------- process(clk_165,rst) begin if clk_165'event and clk_165='1' then RST_LATCHED <= rst; sctn_L1 <= sctn_in; -- counter_data <= c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1; counter_data(9 downto 0) <= c1; counter_data(19 downto 10) <= c1; counter_data(29 downto 20) <= c1; counter_data(39 downto 30) <= c1; counter_data(49 downto 40) <= c1; counter_data(59 downto 50) <= c1; counter_data(69 downto 60) <= c1; counter_data(79 downto 70) <= c1; counter_data(89 downto 80) <= c1; counter_data(99 downto 90) <= c1; counter_data(109 downto 100) <= c1; counter_data(119 downto 110) <= c1; counter_data(129 downto 120) <= c1; counter_data(139 downto 130) <= c1; counter_data(149 downto 140) <= c1; counter_data(159 downto 150) <= c1; counter_regceb_int <= counter_regceb; counter_enable_int <= counter_enable; if RST_LATCHED = '1' then counter_regceb <= '0'; c1 <= (others => '0'); counter_data <= (others => '0'); counter_enable <= '0'; data_load <= '0'; else if actual_diag = '1' then --actual data data_load <= valid_regceb; -- valid_enableL1 <= valid_enable; valid_enableL1 <= valid_enable; valid_dataL1 <= valid_data; else --counter data data_load <= counter_regceb_int; valid_enableL1 <= counter_enable_int; valid_dataL1 <= counter_data; end if; -- if counter_regceb = '1' then -- counter_regceb <= '0'; -- else -- c1 <= c1 + 1; -- counter_regceb <= '1'; -- end if; -- end if; if fout = '1' then counter_enable <= '1'; counter_regceb <= '1'; -- elsif counter_enable = '1' and c1 < 23 and fout = '0' then elsif counter_enable = '1' and c2 < 31 and fout = '0' then c1 <= c1 + 1; c2 <= c2 + 1; -- elsif c1 = 23 and fout = '0' then elsif c2 = 31 and fout = '0' then -- c1 <= c1 + 1; c1 <= (others => '0'); counter_enable <= '0'; counter_regceb <= '0'; c2 <= (others => '0'); end if; end if; end if; end process; --data to ram with delay alignment with data_load process(clk_165) begin if clk_165'event and clk_165='1' then valid_dataL2 <= valid_dataL1; end if; end process; ---This has to changed to the USB latching. -- usb_commandL1 <= usb_command; --------------------------------------------------------------------------------- write_en_gen_inst : write_en_gen port map ( clk_165 => clk_165, data_load => data_load, valid_enable => valid_enableL1, -- latched valid enable rst => rst, fibre_no => fibre_no, no_ch_fibre1 => no_ch_fibre1, no_ch_fibre2 => no_ch_fibre2, no_ch_fibre3 => no_ch_fibre3, no_ch_fibre4 => no_ch_fibre4, rd_complete => rd_complete, --o/ps addra => addra, wr_en1 => wr_en1, wr_en2 => wr_en2, wr_en3 => wr_en3, wr_en4 => wr_en4, start_rd1 => start_rd1, start_rd2 => start_rd2, start_rd3 => start_rd3, start_rd4 => start_rd4 ); --------------------------------------------------------------------------------- ram160_inst1 : ram160 Port map ( clka => clk_165, dina => valid_dataL2, addra => addra, ena => '1', wea => wr_en1, -- clkb => TILE0_TXUSRCLK20, --clk_125, clkb => TILE1_TXUSRCLK20, --clk_125, addrb => addrb1, enb => '1', doutb => ram_data1 ); --********************************* ram160_inst2 : ram160 Port map ( clka => clk_165, dina => valid_dataL2, addra => addra, ena => '1', wea => wr_en2, clkb => TILE0_TXUSRCLK20, --clk_125, addrb => addrb2, enb => '1', doutb => ram_data2 ); --********************************* ram160_inst3 : ram160 Port map ( clka => clk_165, dina => valid_dataL2, addra => addra, ena => '1', wea => wr_en3, -- clkb => TILE1_TXUSRCLK20, --clk_125, clkb => TILE0_TXUSRCLK20, --clk_125, addrb => addrb3, enb => '1', doutb => ram_data3 ); --********************************* ram160_inst4 : ram160 Port map ( clka => clk_165, dina => valid_dataL2, addra => addra, ena => '1', wea => wr_en4, clkb => TILE1_TXUSRCLK20, --clk_125, addrb => addrb4, enb => '1', doutb => ram_data4 ); --********************************* --------------------------------------------------------------------------------- packet_inst1 : packetization Port map ( rst => rst, TX_RST => TILE0TX_RST, -- clk_125 => TILE0_TXUSRCLK20, --clk_125, -- read clk 125Mhz clk_125 => TILE1_TXUSRCLK20, --clk_125, -- read clk 125Mhz clk_165 => clk_165, sctn_in => sctn_L1, -- usb_command => usb_command, -- usb_load => usb_load, sig => "00", --usb_command(2 downto 1), --fibre no start_rd => start_rd1, data_in => ram_data1, -- read data from RAM fibre_no => fibre_no, no_ch_fibre1 => no_ch_fibre1, no_ch_fibre2 => no_ch_fibre2, no_ch_fibre3 => no_ch_fibre3, no_ch_fibre4 => no_ch_fibre4, node_in => node_in, --outputs addrb => addrb1, -- add to ram -- enb => enb1, -- read en to ram rd_complete => rd_complete1, dout => dout1, charisk => charisk1, txchardispmode => txchardispmode1, txchardispval => txchardispval1 ); --********************************* packet_inst2 : packetization Port map ( rst => rst, TX_RST => TILE0TX_RST, clk_125 => TILE0_TXUSRCLK20, --clk_125, -- read clk 125Mhz clk_165 => clk_165, sctn_in => sctn_L1, sig => "01", --usb_command(2 downto 1), --fibre no start_rd => start_rd2, data_in => ram_data2, -- read data from RAM fibre_no => fibre_no, no_ch_fibre1 => no_ch_fibre1, no_ch_fibre2 => no_ch_fibre2, no_ch_fibre3 => no_ch_fibre3, no_ch_fibre4 => no_ch_fibre4, node_in => node_in, --outputs addrb => addrb2, -- add to ram -- enb => enb2, -- read en to ram rd_complete => rd_complete2, dout => dout2, charisk => charisk2, txchardispmode => txchardispmode2, txchardispval => txchardispval2 ); --********************************* packet_inst3 : packetization Port map ( rst => rst, TX_RST => TILE1TX_RST, -- clk_125 => TILE1_TXUSRCLK20, --clk_125, -- read clk 125Mhz clk_125 => TILE0_TXUSRCLK20, --clk_125, -- read clk 125Mhz clk_165 => clk_165, sctn_in => sctn_L1, sig => "10", --usb_command(2 downto 1), --fibre no start_rd => start_rd3, data_in => ram_data3, -- read data from RAM fibre_no => fibre_no, no_ch_fibre1 => no_ch_fibre1, no_ch_fibre2 => no_ch_fibre2, no_ch_fibre3 => no_ch_fibre3, no_ch_fibre4 => no_ch_fibre4, node_in => node_in, --outputs addrb => addrb3, -- add to ram -- enb => enb3, -- read en to ram rd_complete => rd_complete3, dout => dout3, charisk => charisk3, txchardispmode => txchardispmode3, txchardispval => txchardispval3 ); --********************************* packet_inst4 : packetization Port map ( rst => rst, TX_RST => TILE1TX_RST, clk_125 => TILE1_TXUSRCLK20, --clk_125, -- read clk 125Mhz clk_165 => clk_165, sctn_in => sctn_L1, sig => "11", --usb_command(2 downto 1), --fibre no start_rd => start_rd4, data_in => ram_data4, -- read data from RAM fibre_no => fibre_no, no_ch_fibre1 => no_ch_fibre1, no_ch_fibre2 => no_ch_fibre2, no_ch_fibre3 => no_ch_fibre3, no_ch_fibre4 => no_ch_fibre4, node_in => node_in, --outputs addrb => addrb4, -- add to ram -- enb => enb4, -- read en to ram rd_complete => rd_complete4, dout => dout4, charisk => charisk4, txchardispmode => txchardispmode4, txchardispval => txchardispval4 ); --rd_complete syncronization------------------------------------------------------------------------------- process(clk_165) begin if clk_165'event and clk_165 = '1' then if fibre_no = "001" then rd_complete <= rd_complete1; elsif fibre_no = "010" and no_ch_fibre2 < no_ch_fibre1 then rd_complete <= rd_complete1; elsif fibre_no = "010" and no_ch_fibre2 >= no_ch_fibre2 then rd_complete <= rd_complete2; elsif fibre_no = "011" and no_ch_fibre3 < no_ch_fibre2 then rd_complete <= rd_complete2; elsif fibre_no = "011" and no_ch_fibre3 >= no_ch_fibre2 then rd_complete <= rd_complete3; elsif fibre_no = "100" and no_ch_fibre4 < no_ch_fibre3 then rd_complete <= rd_complete3; elsif fibre_no = "100" and no_ch_fibre4 >= no_ch_fibre3 then rd_complete <= rd_complete4; end if; end if; end process; data_load_MON <= data_load; valid_enableL1_MON <= valid_enableL1; ------------------------------------------------------------------------------- end trans;