--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:36:40 02/27/2009
-- Design Name:   trans_test2
-- Module Name:   E:/mwa/MWA_AFGOFIBRE_SIM_FEB08/Packetization_v1/trans_test2_TB.vhd
-- Project Name:  Packetization_v1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: trans_test2
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY trans_test2_TB_vhd IS
END trans_test2_TB_vhd;

ARCHITECTURE behavior OF trans_test2_TB_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT trans_test2
	PORT(
		clk_165 : IN std_logic;
		clk_125 : IN std_logic;
		rst : IN std_logic;
		sctn_in : IN std_logic;
		valid_regceb : IN std_logic;
		valid_data : IN std_logic_vector(159 downto 0);
		usb_command : IN std_logic_vector(31 downto 0);
		usb_load : IN std_logic;          
		dout1 : OUT std_logic_vector(15 downto 0);
		dout2 : OUT std_logic_vector(15 downto 0);
		dout3 : OUT std_logic_vector(15 downto 0);
		dout4 : OUT std_logic_vector(15 downto 0);
		charisk1 : OUT std_logic_vector(1 downto 0);
		charisk2 : OUT std_logic_vector(1 downto 0);
		charisk3 : OUT std_logic_vector(1 downto 0);
		charisk4 : OUT std_logic_vector(1 downto 0);
--		actual_diag : out STD_LOGIC;
		ip_dpram_en : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_165,usb_clk,valid_clk ,stop:  std_logic := '0';
	SIGNAL clk_125 :  std_logic := '0';
	SIGNAL rst :  std_logic := '0';
	SIGNAL sctn_in :  std_logic := '0';
	SIGNAL valid_regceb :  std_logic := '0';
	SIGNAL usb_load :  std_logic := '0';
	SIGNAL valid_data:  std_logic_vector(159 downto 0) := (others=>'0');
	SIGNAL usb_command :  std_logic_vector(31 downto 0) := (others=>'0');

	--Outputs
	SIGNAL dout1 :  std_logic_vector(15 downto 0);
	SIGNAL dout2 :  std_logic_vector(15 downto 0);
	SIGNAL dout3 :  std_logic_vector(15 downto 0);
	SIGNAL dout4 :  std_logic_vector(15 downto 0);
	SIGNAL charisk1 :  std_logic_vector(1 downto 0);
	SIGNAL charisk2 :  std_logic_vector(1 downto 0);
	SIGNAL charisk3 :  std_logic_vector(1 downto 0);
	SIGNAL charisk4 :  std_logic_vector(1 downto 0);
	SIGNAL ip_dpram_en :  std_logic;


	SIGNAL sctn_counter1 : std_logic_vector(23 downto 0):=(others => '0');
	SIGNAL c1,usb,cnt  :  std_logic_vector(9 downto 0):=(others => '0');


BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: trans_test2 PORT MAP(
		clk_165 => clk_165,
		clk_125 => clk_125,
		rst => rst,
		sctn_in => sctn_in,
		valid_regceb => valid_regceb,
		valid_data => valid_data,
		usb_command => usb_command,
		usb_load => usb_load,
		dout1 => dout1,
		dout2 => dout2,
		dout3 => dout3,
		dout4 => dout4,
		charisk1 => charisk1,
		charisk2 => charisk2,
		charisk3 => charisk3,
		charisk4 => charisk4,
--		actual_diag => actual_diag,
		ip_dpram_en => ip_dpram_en
	);


clk_165p: 
process -- Generate clock waveform of 330 MHz
    begin 
    	clk_165<= '1', '0' after 3  ns, '1' after 6 ns, '0' after   9 ns;
    	wait for 12 ns	; 
end process clk_165p; 

clk_125p: 
process -- Generate clock waveform of 125 MHz to be feb to out_test
    begin 
    	clk_125<= '1', '0' after 4  ns, '1' after 8 ns, '0' after   12 ns;
    	wait for 16 ns	; 
end process clk_125p; 

rst <= '1', '0' after 120 ns;




SCTN_p: 
process(clk_165) -- generate clock waveform 
   begin
	 if clk_165'event and clk_165 = '1' then
 			sctn_counter1 <= sctn_counter1 + '1';
		   sctn_in <= '1';
		    if sctn_counter1 = 32767 then --8388608 then
				sctn_in <= '0';
 			   sctn_counter1 <= (others => '0');
			 end if;
	 end if;
end process SCTN_p;	



process(clk_165)
begin
	if clk_165'event and clk_165 = '1' then
	  valid_regceb <= '1';
--	  if valid_regceb = '1' then
--		valid_regceb <= '0';
--	  end if; 	
	end if;
end process;

valid_data <= 	c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1 & c1;





--------------------------------------------------
usb_load_gen: 
process(clk_165) -- generate clock waveform 
   begin
	 if clk_165'event and clk_165 = '1' then
 			usb <= usb + '1';
	 end if;
end process usb_load_gen;	
usb_clk <= usb(1);
valid_clk <= usb(0);

process(valid_clk)
begin
 if valid_clk'event and valid_clk = '1' then
		   c1 <= c1 - '1' ; 
 end if;
end process; 


process(usb_clk)
begin
	if usb_clk'event and usb_clk = '1' then
  if stop = '0' then	  
	  cnt <= cnt + '1';
     if cnt < 5 then
	   usb_load <= '0';
	  elsif cnt > 4 and cnt < 8   then	  	
	   usb_load <= '1';
     else  
		usb_load <= '0';
		stop <= '1';
	  end if; 	
  end if;  

-------------------------------------------------------------
--USB COMMAND SELECTION:
--23 - 16  : Node no
--15   	  : Actual or counter data selection bit 
--14 - 12  : No of chs in Fibre 4 
--11 - 9   : No of chs in Fibre 3 
--8 - 6    : No of chs in Fibre 2
--5  - 3   : No of chs in Fibre 1
--2  - 0   : Fibre no

-------------------------------------------------------------
--	usb_command	 <=  X"003F0001"; -- 1chs 1st fibre
--	usb_command	 <=  X"003F007A"; --10chs
--	usb_command	 <=  X"003F01FA"; -- 16chs
--	usb_command	 <=  X"003F07FB"; -- 20chs
	usb_command	 <=  X"003F0FFB"; -- 24chs
--	usb_command	 <=  X"003F5FFC"; -- 30chs
--	usb_command	 <=  X"003F6FFC"; -- 31chs
--	usb_command	 <=  X"003FFFFC"; -- 32chs
	

	end if;
end process;


END;