-------------------------------------------------------------------------------
--$Date: 2007/08/01 23:10:49 $
--$RCSfile: tx_sync_vhd.ejava,v $
--$Revision: 1.1.2.1 $
-------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 1.7
--  \   \         Application : GTP Wizard 
--  /   /         Filename : tx_sync.vhd
-- /___/   /\     Timestamp : 
-- \   \  /  \ 
--  \___\/\___\ 
--
--
-- Module TX_SYNC
-- Generated by Xilinx GTP Wizard

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity TX_SYNC is
port
(
    TXENPMAPHASEALIGN    :   out    std_logic; 
    TXPMASETPHASE    :   out    std_logic; 
    SYNC_DONE        :   out    std_logic;  
    USER_CLK         :   in     std_logic;  
    RESET                :   in     std_logic 
);
end TX_SYNC;

architecture RTL of TX_SYNC is
--***********************************Parameter Declarations********************

    constant DLY : time := 1 ns;

--*******************************Register Declarations************************

    signal  begin_r               :   std_logic;
    signal  phase_align_r         :   std_logic;
    signal  ready_r               :   std_logic;
    signal  sync_counter_r        :   unsigned(14 downto 0);
    signal  wait_before_sync_r    :   unsigned( 9 downto 0);
    signal  wait_stable_r         :   std_logic;
    
--*******************************Wire Declarations****************************
    
    signal   count_512_complete_r :   std_logic;
    signal   next_phase_align_c   :   std_logic;
    signal   next_ready_c         :   std_logic;
    signal   next_wait_stable_c   :   std_logic;
    signal   sync_count_complete_r:   std_logic;

begin
--*******************************Main Body of Code****************************

    --________________________________ State machine __________________________    
    -- This state machine manages the phase alingnment procedure of the GTP.
    -- The module is held in reset till the usrclk source is stable.In the 
    -- case of buffer bypass where the refclkout is used to clock the usrclks,
    -- the usrclk stable indication is given the pll_locked signal.
    -- Once the pll_lock is asserted, state machine goes into the wait_stable_r
    -- for 512 cycles to allow some time to ensure the pll is stable. After this, 
    -- it goes into the phase_align_r state where the phase alignment procedure is 
    -- executed. This involves asserting the TXENPHASEALIGN and TXPMASETPHASE for 
    -- the recommended number of clock cycles
    
    -- State registers
    process( USER_CLK )
    begin
        if(USER_CLK'event and USER_CLK = '1') then
            if(RESET='1') then
                begin_r           <=  '1' after DLY;
                wait_stable_r     <=  '0' after DLY;
                phase_align_r     <=  '0' after DLY;
                ready_r           <=  '0' after DLY;
            else
                begin_r           <=  '0' after DLY;
                wait_stable_r     <=  next_wait_stable_c after DLY;
                phase_align_r     <=  next_phase_align_c after DLY;
                ready_r           <=  next_ready_c after DLY;
            end if;
        end if;
    end process;

    -- Next state logic
    next_wait_stable_c      <=   begin_r or
                                 (wait_stable_r and not count_512_complete_r);
                                        
    next_phase_align_c      <=   (wait_stable_r and count_512_complete_r) or
                                 (phase_align_r and not sync_count_complete_r);
                                        

    next_ready_c            <=   (phase_align_r and sync_count_complete_r) or
                                 ready_r;



    --_________ Counter for to wait for pll to be stable before sync __________
    process( USER_CLK )
    begin
        if(USER_CLK'event and USER_CLK = '1') then
            if (wait_stable_r='0') then
                wait_before_sync_r <= (others=>'0') after DLY;
            else
                wait_before_sync_r <= wait_before_sync_r + 1 after DLY;
            end if;
        end if;
    end process;

    count_512_complete_r <= wait_before_sync_r(9);

    --_______________ Counter for holding SYNC for SYNC_CYCLES ________________
    process( USER_CLK )
    begin
        if(USER_CLK'event and USER_CLK = '1') then
            if (phase_align_r='0') then
                sync_counter_r <= (others=>'0') after DLY;
            else
                sync_counter_r <= sync_counter_r + 1 after DLY;
            end if;
        end if;
    end process;

    sync_count_complete_r <= sync_counter_r(12);

    --_______________ Assign the phase align ports into the GTP _______________

    TXENPMAPHASEALIGN <= not begin_r;
    TXPMASETPHASE     <= phase_align_r;

    --_______________________ Assign the sync_done port _______________________
    
    SYNC_DONE <= ready_r;
    
    
end RTL;